ADIS16203 : Latency until updating data register

Hello,

I'd like to know the latency of ADIS16203.
I have heard that the ADI's MEMS sensors are using sigma-delta adc usually.
So I am guessing the ADIS16203 is same.
Also the ADIS16203 has digital filter.

I'd like to know the formula for computation for latency which is from changing angle until updating data register(INCL_OUT and INCL_180_OUT).
Would you please indicate the formula of latency ?


Best regards,
ysuzuki

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  • Hello Mark,

    I'm sorry, there are circumstances, I would like to know the latency of Analog to Digital conversion only.
    If ADIS16203 uses SAR ADC, the latency will be consists from sample interval and filter delay.
    If ADIS16203 uses sigma-delta ADC, the latency will depend on the clock for sigma-delta modulator and the length(number of tap) of decimation filter.

    I'd like to know about the following information.

    1. ADC architecture for ADIS16203. (SAR or Sigma-delta ?)
    2. If ADIS16203 uses SAR,
       Latency of digital filter for INCL_OUT. (until updating data register)
        Conditions:
          SMPL_TIME=0x01 ... cinversion time is 244.2us
          AVG_CNT=0x01   ... N=2
    3. If ADIS16203 uses Sigma-delta ADC,
       Total latency. (until updating data register)
       It will be consists from decimation filter and digital filter for INCL_OUT.
        Conditoins:
          SMPL_TIME=0x01 ... cinversion time is 244.2us
          AVG_CNT=0x01   ... N=2


    Best regards,
    ysuzuki

Reply
  • Hello Mark,

    I'm sorry, there are circumstances, I would like to know the latency of Analog to Digital conversion only.
    If ADIS16203 uses SAR ADC, the latency will be consists from sample interval and filter delay.
    If ADIS16203 uses sigma-delta ADC, the latency will depend on the clock for sigma-delta modulator and the length(number of tap) of decimation filter.

    I'd like to know about the following information.

    1. ADC architecture for ADIS16203. (SAR or Sigma-delta ?)
    2. If ADIS16203 uses SAR,
       Latency of digital filter for INCL_OUT. (until updating data register)
        Conditions:
          SMPL_TIME=0x01 ... cinversion time is 244.2us
          AVG_CNT=0x01   ... N=2
    3. If ADIS16203 uses Sigma-delta ADC,
       Total latency. (until updating data register)
       It will be consists from decimation filter and digital filter for INCL_OUT.
        Conditoins:
          SMPL_TIME=0x01 ... cinversion time is 244.2us
          AVG_CNT=0x01   ... N=2


    Best regards,
    ysuzuki

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