ADIS16460 SYNC

hi

i am thinking to use the adis16460 with external clock to synchronize it with my control loop (Direct Sample Control MODE), i will be happy if you can please explain me about how this effects system performance  as i came across the next line: 

"The sync input clock functions below the specified minimum value but at reduced performance levels" ?

i am planning to provide a 2kHz clock signal, so i assume that the low pass filter configuration (as seen in figure 29) will be all most the same as 2KHZ is very close to the default 2048Hz , is that assumption correct?

best regards

Mark

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    •  Analog Employees 
    on Aug 29, 2016 11:07 PM over 4 years ago

    Thank you! Just to be sure, is this in the default configuration for data ready? MSC_CTRL[0] = 1?  Is the CRC correct every time?  It appears like the burst read request is delaying the internal routine's execution of the register update at times.  As long as the SCLK does not exceed 1MHz, this should not influence the actual sample rate.  I will forward this to a colleague who may have tested this particular scenario (I have not, unfortunately), in parallel with your feedback on the MSC_CTRL contents.

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  • 0
    •  Analog Employees 
    on Aug 29, 2016 11:07 PM over 4 years ago

    Thank you! Just to be sure, is this in the default configuration for data ready? MSC_CTRL[0] = 1?  Is the CRC correct every time?  It appears like the burst read request is delaying the internal routine's execution of the register update at times.  As long as the SCLK does not exceed 1MHz, this should not influence the actual sample rate.  I will forward this to a colleague who may have tested this particular scenario (I have not, unfortunately), in parallel with your feedback on the MSC_CTRL contents.

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