ADIS16460 SYNC

hi

i am thinking to use the adis16460 with external clock to synchronize it with my control loop (Direct Sample Control MODE), i will be happy if you can please explain me about how this effects system performance  as i came across the next line: 

"The sync input clock functions below the specified minimum value but at reduced performance levels" ?

i am planning to provide a 2kHz clock signal, so i assume that the low pass filter configuration (as seen in figure 29) will be all most the same as 2KHZ is very close to the default 2048Hz , is that assumption correct?

best regards

Mark

  • 0
    •  Analog Employees 
    on Aug 23, 2016 6:22 PM over 4 years ago

    Thank you for your post. We would not anticipate major changes in performance when using 2000Hz clocks. That note was meant to discourage those who might be tempted to offer much lower clock rates, which could under-sample the sensor responses. 

  • Hi Mark

    thank you very much for your reply.

    i have established connection with the device  using the burst mode and everything works well.

    in my application program i have an a 2Khz control loop, and i want to synchronize it to the data ready time in ADIS16460 , so i will have small and constant time delay.

    i will be happy if you can help with the next  issues:

    - i have monitored the DR pin with scope , and it seems that the act of reading the output registers influence on the internal sample process: for example if i use the default settings (2048SPS) and i read the data in 2khz rate i see the time period on the DR signal slightly changes - meaning the the frequency isnt constant but moves around 2KHz , does the act of reading sensor data influence the sensor internal sampling process?

    - about using the external clock, if i provide a 2Khz PWM signal (with 50% duty cycle) i assume that the internal sampling rate will be also 2KHz is my assumption correct? 

    best regards

    Mark

  • 0
    •  Analog Employees 
    on Aug 28, 2016 6:57 PM over 4 years ago

    The Stall period and Read rate specifications(Table 2, ADIS16460 Datasheet) are in place to prevent influencing the sample rate, but I might need to do a little research to see if your specific scenario was tested during characterization.  Could you quantify the level of change you are observing, along with your method of observation?  Are you reading the data in Burst mode or through individual requests?

  • hi Mark

    i am using the Burst mode , i have a 2khz interrupt - every 500us i read the output registers.

    and monitoring the DR pin

    this IMAGE is chip select vs clock:

     

    this IMAGE is chip select vs DR pin:

    this IMAGE is chip select vs DR pin (with scope stoped):

  • 0
    •  Analog Employees 
    on Aug 29, 2016 11:07 PM over 4 years ago

    Thank you! Just to be sure, is this in the default configuration for data ready? MSC_CTRL[0] = 1?  Is the CRC correct every time?  It appears like the burst read request is delaying the internal routine's execution of the register update at times.  As long as the SCLK does not exceed 1MHz, this should not influence the actual sample rate.  I will forward this to a colleague who may have tested this particular scenario (I have not, unfortunately), in parallel with your feedback on the MSC_CTRL contents.