ADIS16210

Dear supporter

Using the ADIS16210 controlled by an FPGA with the below pseudo code of VHDL driver:

Spi_clk frequency = 500KHz

Cs = 1

Clk = 1

Upon request from software to read data from a register (address 0x5600, rdn_wr bit is 0):

 

Cs = 0

Wait 1 us (Tcs)

Enable clk

                Loop (16 times)

Wait for falling edge of clk

Send 1 bit of address (msb first)

End loop

Disable clk

Cs = 1 

 

Wait gap time (50 us)

Cs = 0

Wait 2 us (Tcs)

Enable clk

 

                Loop (16 times)

Wait for rising edge of clk

read 1 bit of address (msb first) 

End loop 

Disable clk 

Cs = 1  

Signal the software that data is ready.

Reading the 0x5600 register in loop, (as figure 6 in data sheet) we get most of the time the expected result but from time to time we get a "000" read data.

Timing were verified and found fitting the spec.

Pls advise what are we missing?

Thanks

Freddy