What is the relationship between the user selectable output data rate and the ADC sampling period? Is it fixed or does it vary?
ADXL345
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The ADXL345 is a small, thin, low power, 3-axis accelerometer with high resolution (13-bit) measurement at up to ±16g. Digital output data is formatted...
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ADXL345 on Analog.com
What is the relationship between the user selectable output data rate and the ADC sampling period? Is it fixed or does it vary?
The short answer is that it depends on the data rate. The long answer is:
At ODR=3200Hz the output is the direct ADC output.
At ODR=1600Hz you still get direct ADC output, but the ADC is clocked so as to skip every other read cycle (this saves power as we shut the ADC down during skipped cycles)
At ODR=800Hz to 100Hz the ADC is sampling at 3200Hz and the ADC output goes through a digital filter with varying coefficients to result in different bandwidths.
At ODR<100Hz the ADC still runs at 3200Hz, we just skip more measurement cycles. The effective bandwidth is 50Hz (same as the 100Hz ODR), but with less frequent reporting. Again, this is done to save power. You can see the current consumption reduce as bandwidth is reduced below 100Hz ODR.
The short answer is that it depends on the data rate. The long answer is:
At ODR=3200Hz the output is the direct ADC output.
At ODR=1600Hz you still get direct ADC output, but the ADC is clocked so as to skip every other read cycle (this saves power as we shut the ADC down during skipped cycles)
At ODR=800Hz to 100Hz the ADC is sampling at 3200Hz and the ADC output goes through a digital filter with varying coefficients to result in different bandwidths.
At ODR<100Hz the ADC still runs at 3200Hz, we just skip more measurement cycles. The effective bandwidth is 50Hz (same as the 100Hz ODR), but with less frequent reporting. Again, this is done to save power. You can see the current consumption reduce as bandwidth is reduced below 100Hz ODR.