Hi,
I am using an ADXL375 on SPI (4-wire, CPOL=1, CPHA=1, DMA, CS deasserted between
transactions). FIFO is in bypass, BW_RATE = 0x0E (1600 Hz), DATA_FORMAT = 0x0F. I read
registers 0x32–0x37 in a single multi-byte read every 250 µs, so about 2.4 reads per
sample.
About one read in 1.75 million comes back corrupted. The pattern is always the same: the
bytes are the correct value with some '1' bits missing, never with extra bits set. For
example DATAZ1 should be 0xFF and instead I get 0x80, 0x84, 0x94, 0xB4 or 0xF7 – nothing
else, and those five values form a strict nested chain. It looks to us like a register
write that I caught before it finished.
I am fairly sure it is not on my side. No OVR, no MODF, no DMA error and NDTR = 0 in 45
million reads. Halving the SPI clock from 5.25 to 2.625 MHz changed neither the rate nor
the number of corrupted bits, so it does not look like an analogue timing issue. It
reproduces on many different boards. Also, the corrupted byte comes back to us on SDO
during the command byte of the next transaction, so it really was on the pin.
my questions:
1. During a multi-byte read in bypass mode, is there a window at the start of the burst
where an internal ODR update can be captured while the data registers are only
partially loaded?
2. Does DATA_READY (INT_SOURCE D7) assert strictly after the registers are fully updated?
I want to gate my reads on it, so this decides whether it helps.
3. Is gating on DATA_READY the recommended approach in bypass mode when the host reads
faster than the ODR? Should I use FIFO stream mode instead?
One more thing. I also have an ADXL357 in the same system, read the same way (2000 Hz
ODR, 4 kHz reads, no DRDY gating, no FIFO) and I have never seen this on that part. Are
the acceleration registers 0x08–0x10 protected during a multi-byte read? The datasheet
says the temperature registers are not double buffered, which made us think the
acceleration path is, but I could not find it stated anywhere.
Thanks,
