About CLK Frequency of ADXL366

Question

Hi, 
 Please tell me about the CLK frequency of the ADXL366. Is it possible to use an 8 MHz clock for SPI communication under VDD 1.8 V conditions? 
 
 VDD 2V: 8 MHz 1.2V < VDDIO < 1.4V: 5 MHz 1.1V < VDDIO < 1.2V: 2.5 MHz The specifications listed above are available, but could you please provide the clock specifications for the 1.8V operating condition? 
 
 Best Regards,

nimejia · Accepted Answer

Hi there, thanks for your question. I've spoken to the evaluation team and they have told me that SPI can run at 8 MHz under these conditions, but a high clock speed may introduce an offset to the output if there is another device on the SPI bus streaming at significantly higher speeds than the XL366. If this is the case for your application, it may be worth following the SPI bus sharing layout example from the datasheet: 
 
 Hope this is helpful to your design process. 
 Regards, 
 Nico)

SLA Status	Assignee	Support Status
SLA Closed. Met after 55 hours		Open

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About CLK Frequency of ADXL366

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