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Internal clock drift over temperature and time

Category: Hardware
Product Number: ADXL355

Hello everybody,

I have a setup with eight distributed ADXL355 acceleration sensors. These are mounted in housings outdoors (-20 degrees to +50 degrees). Over a longer measurement period (currently half an hour), I have different numbers of samples for all sensor boxes. I would explain this with different internal clock frequencies and thus different sampling rates (data sheet Rev. D Fig. 52).

I have two questions about this:

  • How much does the clock frequency change with temperature, and is there a characteristic curve for this?
  • Does data sheet Rev. D Fig. 52 refer to the distribution of clock frequencies across several manufactured ADXL355s or the distribution over time? If it refers to the distribution across several ADXL355s, are there also diagrams showing stability over time?
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  • Hi there, thanks for the question. Temperature does indeed have an effect on clock speed, but it should not be very large. Could you provide us with more information on the differences in number of samples? Per our calculations, at 4 kHz ODR, a device is expected to output 7,200,000 samples over a time period of a half hour. However, there is a variation of up to ±1.2% over the device's rated temp range of -40 to 125C, as seen at the top of page 13 of the datasheet. Figure 52 also shows the clock speed of different devices under test (DUTs), and is intended to show the expected variation due to the silicon lottery. Per my calculations, factoring in clock variations due to temperature and the manufacturing process, you should expect a variation in number of samples of up to ±2.2%; for the number of samples taken at max ODR over a half hour, this works out to around 7,042,000 to 7,360,000 samples. If the sample sizes are within this range (I'm assuming you are working at max ODR here but correct me if I'm wrong), the variation can be explained by this, but if the variation is larger, then it is another issue. If you could share more information about your setup and the variation in sample sizes you are getting I could help you work through this.

     

    Thanks,

    Nicolás

Reply
  • Hi there, thanks for the question. Temperature does indeed have an effect on clock speed, but it should not be very large. Could you provide us with more information on the differences in number of samples? Per our calculations, at 4 kHz ODR, a device is expected to output 7,200,000 samples over a time period of a half hour. However, there is a variation of up to ±1.2% over the device's rated temp range of -40 to 125C, as seen at the top of page 13 of the datasheet. Figure 52 also shows the clock speed of different devices under test (DUTs), and is intended to show the expected variation due to the silicon lottery. Per my calculations, factoring in clock variations due to temperature and the manufacturing process, you should expect a variation in number of samples of up to ±2.2%; for the number of samples taken at max ODR over a half hour, this works out to around 7,042,000 to 7,360,000 samples. If the sample sizes are within this range (I'm assuming you are working at max ODR here but correct me if I'm wrong), the variation can be explained by this, but if the variation is larger, then it is another issue. If you could share more information about your setup and the variation in sample sizes you are getting I could help you work through this.

     

    Thanks,

    Nicolás

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