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ADXL382 Application FIFO Example Watermark

Category: Software
Product Number: adxl382

Hi,
I have a question on the following section of the adxl38x fifo example under
https://github.com/analogdevicesinc/no-OS/blob/main/projects/eval-adxl38x/src/examples/fifo_example/fifo_example_main.c

while (true) {
		// Read status to assert if FIFO_WATERMARK bit set
		ret = adxl38x_read_device_data(adxl38x_desc, ADXL38X_STATUS0, 1, &status0);
		if (ret)
			goto error;
		pr_info("Status 0: %d\n", status0);
		ret = adxl38x_read_device_data(adxl38x_desc, ADXL38X_FIFO_STATUS0, 2,
					       fifo_status);
		if (ret)
			goto error;
		fifo_entries = no_os_get_unaligned_le16(fifo_status);
		fifo_entries = fifo_entries & 0x01ff;


		// Read FIFO status and data if FIFO_WATERMARK is set
		if (status0 & NO_OS_BIT(3)) {
			pr_info(" FIFO_WATERMARK is set. Total fifo entries =  %d\n", fifo_entries);
			if (fifo_entries < set_fifo_entries)
				goto unmatch_error;

This loop basically checks for the WATERMARK Bit in the status register. Why is there an unmatch error check after detecting the set WATERMARK Bit? By definition, the watermark bit should only be set when the desired amount of samples is reached in the fifo.
Why is this check needed?

In Addition:
In my implementation I noted, that after detecting the watermark bit as set, the number of fifo entries given by the FIFO_STATUS0 register is sometimes one sample behind.

For example:
Watermark threshold is set to 9 entries. After detecting that the watermark bit is set I immediately read the number of fifo entries from FIFO_STATUS0 register --> this yields only 6 samples.

Thank you

  • Hello  the support team will have limited availability this week. Besides I have no ownership on this part here you have some early comments:

    - What do you mean with sometimes?

    In Addition:
    In my implementation I noted, that after detecting the watermark bit as set, the number of fifo entries given by the FIFO_STATUS0 register is sometimes one sample behind.


    This behavior remains with different working modes (one axis output by example), ODRs or configurations? What happens when you leave some ms delay between the watermark and the status read?

    best regards,

    Mario SM

  • Hello Mario,

    Sometimes means that the behavior is kind of random. In my application, I´m capturing for a duration of 5 seconds. In some measurements this behavior is not present, in some measurements it happens that I´m running into a unmatch error.

    I can fix the issue by adding a delay of about 10us between reading STATUS_0 register and FIFO_STATUS register. Does that mean, that there is a delay between the watermark bit being set and the number of fifo entries updated?

    The questions remains why checking the number of available fifo entries is necessary when the watermark bit is already set.

    Is there a problem with just checking for the watermark bit and then directly reading from the fifo?