I’m experimenting with an ADXL1005 accelerometer (ADXL1005 (Rev. 0)) and trying to reconcile its output-load stability note with the EVAL-ADXL1005Z schematic filter.
Datasheet rule:
-
“Output amplifier is stable while driving capacitive loads up to 100 pF directly (no series resistor).”
-
“For capacitive loads > 100 pF, add a series resistor ≥ 8 kΩ.”
-
“Output capacitance must not exceed 22 nF.”
Eval board filter:
Vout ── R1 ──●── R2 ──●──> to rest of chain
│ │
C1 C2
│ │
GND GND
With R1 = 487 Ω, R2 = 976 Ω, C1 = C2 = 3.9 nF.
So there are caps on the order of nF, but they're behind resistors, not tied directly to Vout.
So what I understand (and where I'm stuck)
For a single branch of the filter:
The equivalent capacitance at ω:
Ceq(ω)=C / (1+(ωCR_s)^2)
Load angle ∠Z = -arctan(1/(ωCR_2))
I can then compute Ceq and load angle:
At 70kHz (close to the datasheet's small-signal output bandwidth)
Ceq = 1.65 nF and ∠Z = -29°
So C_eq is much larger than 100pF, but the phase angle is far from -90° because the series resistors add a substantial real part. This seems to be why the eval network is stable in practice. (Maybe?)
Q1 (Main): The datasheet’s 100 pF rule is clearly for a capacitor physically tied to Vout. When caps sit behind hundreds of ohms (like R1/R2 above), what is the recommended stability check on the load as “seen” at the pin?
-
Is a criterion like “∠Z > -45°" at some check frequency fcf_cfc (say 70–100 kHz) a reasonable rule of thumb?
Q2 (Finding the “break point”):
Thought experiment: let R1 → 0 Ω with the filter above. By the Intermediate Value Theorem, there must be some R1 where the load becomes “too capacitive” and stability is lost.
How do I compute that boundary from the datasheet info?
Does anyone have a better phase-margin-aware criterion ADI would implicitly be using?
