I am using an nRF series CPU to communicate with the EVAL-ADPD4100-ARDZ development board via SPI. IOVDD is set to 3.3V, and AVDD, DVDD1, and DVDD2 are set to 1.8V.
The following register configurations have been written to the ADPD4100.
0009 0080 # 32MHz trim - trim your own clock
000B 02B2 # 1MHz trim - trim your own clock
000C 0012 # 32kHz trim - trim your own clock
000D 2710 # 100 Hz
000F 0006 # enable 1MHz osc
0010 0000 # one timeslot
0020 0004 # in1 connected to vc1 during sleep, everything else floating
0021 0000 # all inputs single ended, vc1 set to Vdd during sleep
0022 0003 # gpio0 is output, inverted
0023 0002 # intx to gpio0
0014 8000 # fifo thresh interrupt to intx
## timeslot A - continuous connect mode - green PPG
0100 0000 # Rin = 500, tsA offset = 0, skip subsample
0101 40DA # path = TIA + BPF + INT + ADC
0102 0001 # IN1 to channel 1, others disconnected
0103 5002 # precondition inputs to TIA_Vref, VC1 active state = V_delta
0104 03C0 # Rf = 200k Rint = 400k
0105 0707 # 11 mA on LED1A, 2A, 3A
0106 0007
0107 0140 # 64 pulses
0108 0000 # period set by automatic period of continuous connect mode
0109 0210 # led width= 2us led offset=16 us
010A 0003 # integrator width=3 us
010B 0210 # integrator offset=16.5 us - ADJUST FINE OFFSET
010C 0001 # no modulation
0110 0003 # signal size = 3 bytes
010D 0099 # -++- int pattern
010E 0000 # NO OFFSET - review if needed
010F 0000 # NO OFFSET - review if needed
0112 0000 # no decimation
The chip is able to correctly read back the Chip ID and the following register configurations
0009 0080 # 32MHz trim - trim your own clock
000B 02B2 # 1MHz trim - trim your own clock
000C 0012 # 32kHz trim - trim your own clock
000D 2710 # 100 Hz
000F 0006 # enable 1MHz osc
0010 0000 # one timeslot
0020 0004 # in1 connected to vc1 during sleep, everything else floating
0021 0000 # all inputs single ended, vc1 set to Vdd during sleep
0022 0003 # gpio0 is output, inverted
0023 0002 # intx to gpio0
0014 8000 # fifo thresh interrupt to intx
However, all registers in Timeslot A read back as 0x0000 and cannot be written correctly.
I performed additional tests: after enabling both timeslots A and B and writing configurations to their respective registers, I found that the registers for Timeslot B can be written and read back correctly.