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Time to empty FIFO in strean mode

Category: Hardware
Product Number: ADXL375

Hi all,

I set the FIFO watermark level to 15, and ODR at 3200Hz, which makes a sample every 312.5us.The INT0 is the watermark interrupt pin.

As you can see we take 346us to:

  • retrieve number of fifo entries by reading the FIFO_STATUS register 0x39
  • empty 15 samples

which is more than 312.5us.

My question is : Do we lose a sample ?

  • Hello  

    thanks for posting let me find some gap of time to analyze your inquiry, could I get the complete register configuration?

    regards,

    Mario SM

  • Yes of course:

    Device ID        (0x00) = 0xE5
    THRESH_SHOCK     (0x1D) = 0x00
    OFSX             (0x1E) = 0x00
    OFSY             (0x1F) = 0x00
    OFSZ             (0x20) = 0x00
    DUR              (0x21) = 0x00
    Latent           (0x22) = 0x00
    Window           (0x23) = 0x00
    THRESH_ACT       (0x24) = 0x03
    THRESH_INACT     (0x25) = 0x00
    TIME_INACT       (0x26) = 0x00
    ACT_INACT_CTL    (0x27) = 0x00
    SHOCK_AXES       (0x2A) = 0x00
    ACT_SHOCK_STATUS (0x2B) = 0x00
    BW_RATE          (0x2C) = 0x0F
    POWER_CTL        (0x2D) = 0x00
    INT_ENABLE       (0x2E) = 0x02
    INT_MAP          (0x2F) = 0x10
    INT_SOURCE       (0x30) = 0x00
    DATA_FORMAT      (0x31) = 0x0B
    FIFO_CTL         (0x38) = 0x8F
    
    Start measurment:
    =>POWER_CTL      (0x2D) = 0x08

  • Hi  ,

    I posted the configuration. Did you have time to analyze my inquiry?

  • Hello  thanks for your patience.

    After checking the configuration I am not sure if I am following your scope or there is a little misunderstanding;

    -You are working on "Stream mode" (Pg-11 ADXL375 DS) but you are checking the status register. (0x39) This register and the bit D7 within it (FIFO_TRIG) are only related with the "Trigger Mode" (Pg-12 DS). Since you are working with the Stream mode, you should ignore the register 0x39.

    -If I am not mistaken, you are asking about a system limitation in which you can only read data (15 samples) every 346 us, this should not limit the application at first sight, because if you are able to process the whole batch of 15 samples within those 346 us, you have plenty of sampling time space available, until the 17 following 312 us samples fill the FIFO (32 samples space) and you start to lose information.

    In any case if you are worried about loosing data you should check the register 0x30 INT_SOURCE bit D0 Overrun (Pg-23 DS). With your current configuration you are only getting an interruption when you reach the 15 samples watermark limit, which should be enough to avoid data lost if your system retrieves the FIFO info within the times specified above.

    I may also recommend you to follow Pg-23 DS recommendation of configure reg 0x2F before 0x2E.




    Let me know if this solves your problem, and have a nice day

    Mario SM

  • Hi  ,

    It was just a dump of registers, The order of registers configuration is set according to DS.

    You have responded about the system limitation, thanks.