I'm using ADXL357BEZ with External Synchronization and External Clock, No Interpolation Filter.
The datasheet states, "The external clock frequency on INT2 (Pin 13, see Table 15) must be 1.024 MHz."
The datasheet states elsewhere that "All figures include data for multiple devices and multiple lots, and they were taken in the ±10 g range and TA = 25°C, unless otherwise noted. For Figure 52 and Figure 76 , the ODR is derived from a main clock, with a frequency of 1.024 MHz and ±1.4% device to device variation (similar to ODR device to device variation). For a given device, however, clock frequency variation over the temperature range (−40°C to +125°C) is no more than ±1.2%, guaranteed by design."
If I'm supplying an external clock should I interpret the datasheet as requiring an external clock with a frequency of 1.024 MHz +- 1.4%?
As a related question, the datasheet states: " The phase of SYNC must meet an approximate 25 ns setup time to the external clock rising edge." Is it known what the effect is if the 25 ns setup time is not met?
