About supply current to ADIS16137

Thank you for your post in this forum.  I think that it is good to anticipate this as a point of risk, but I wonder if I fully understand your question. 

Forgive me if I am misunderstanding, but the purpose of the 400mA references was to establish a requirement for your system, NOT raise concern need to review the internal regulator's efficiency or load regulation.  

Based on my experience, the two most common problems can be addressed by attention to these points of interest: 

1. During initial ramp, make sure that charging the capacitance on the node is a ramp that is void of negative transients.  This means that "wrap around" current limit schemes, which cannot provide constant current during such charging, should be avoided.  
2. Manage the transient current when the internal processor and other functions, initialize.  Here is a plot, from our initial characterization of this product family. The purple trace exhibits the 400mA peak, along with the time profile.  Power supplies do not always provide clear ratings for this type of event, but based on my experience: 
   1. Adding 25% of margin, on top of stated transient peak, for continuous current supply means that you can use the transient load regulation plots, from power supply datasheets, to make sure that this dip does not drop below 4.75V. 
   2. If the mechanical constraints for managing the thermal load threaten system size/weight objectives, then you might be able to work with your power supply provider to understand the source impedance of supply, which is often the primary point of consideration in short-duration transients.   

Does this help? 

Thank you for your post in this forum.  I think that it is good to anticipate this as a point of risk, but I wonder if I fully understand your question. 

Forgive me if I am misunderstanding, but the purpose of the 400mA references was to establish a requirement for your system, NOT raise concern need to review the internal regulator's efficiency or load regulation.  

Based on my experience, the two most common problems can be addressed by attention to these points of interest: 

1. During initial ramp, make sure that charging the capacitance on the node is a ramp that is void of negative transients.  This means that "wrap around" current limit schemes, which cannot provide constant current during such charging, should be avoided.  
2. Manage the transient current when the internal processor and other functions, initialize.  Here is a plot, from our initial characterization of this product family. The purple trace exhibits the 400mA peak, along with the time profile.  Power supplies do not always provide clear ratings for this type of event, but based on my experience: 
   1. Adding 25% of margin, on top of stated transient peak, for continuous current supply means that you can use the transient load regulation plots, from power supply datasheets, to make sure that this dip does not drop below 4.75V. 
   2. If the mechanical constraints for managing the thermal load threaten system size/weight objectives, then you might be able to work with your power supply provider to understand the source impedance of supply, which is often the primary point of consideration in short-duration transients.   

Does this help?