ADXL355
Recommended for New Designs
The analog output ADXL354 and the digital output ADXL355 are low noise density, low 0 g offset drift, low power, 3-axis accelerometers with selectable...
Datasheet
ADXL355 on Analog.com
Hi,
I am starting to develop a project to manage a chain of ADXL355 sensors connected on a synchronous bus.
Therefore, I need the acquisition of all sensors to occur simultaneously with respect to the external clock (1024 Khz) and external sync.
It is not clear in the data sheet whether in the two modes with external clock and sync, the chip uses the external clock for acquisition instead of the internal clock.
Can you confirm that this is the case?
In other words, when external clock and external sync are enabled:
In my application, the external clock is generated by a VCXO synchronized with the PPS (Pulse Per Second) coming from a GPS, and the design needs to ensure that the acquisition of the various sensors occurs with a phase error on the order of a microsecond.
Thank you, Raffaele