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ADIS16475 vs GPS

Category: Hardware
Product Number: ADIS16475

HI

My client is considering adopting ADIS16475.
The client wants to input 1 Hz signal and synchronize ADIS16475.
The client thinks it can be achieved by inputting 1 Hz pulse into SYNC pin and using “Scaled Sync Mode.”
During the test run, Clock error status appears frequently.
The datasheet says "adjust the frequency of the clock signal," but this is not realistic.
I think I will adjust by adding or subtracting UP_SCALE =KECSF, is this wise?
I would appreciate some advice.

Thank you and best regards,

Parents
  • Can we ask them to share more details about their observation?

    1. Using data ready signal to drive data collection?
    2. DEC_RATE setting? 
    3. How often are they observing the error flag? (once a day vs once a minute vs 50 times/second?)
  • I will answer your question.

    Q1:Using data ready signal to drive data collection?
    A1:No.Currently, I am trying to read data at a constant cycle regardless of the DR state.

    Q2:DEC_RATE setting? 
    A2:DEC_RATE=0x0000

    Q3:How often are they observing the error flag? (once a day vs once a minute vs 50 times/second?
    A3:What was actually confirmed was a cycle of 10ms and 100ms.
     In several minutes of trials, I observed clock errors at a frequency of just under 90% for 10ms cycles and less than 10% for 100ms cycles.

  • Thank you for the updated information.  Are you in a position to measure the nominal (mean) frequency of the resultant data ready signal?  You might want to adjust the UP_SCALE accordingly, so that the nominal frequency is 2000Hz.  Can you try that and let us know if that reduces or eliminates the errors? 

Reply
  • Thank you for the updated information.  Are you in a position to measure the nominal (mean) frequency of the resultant data ready signal?  You might want to adjust the UP_SCALE accordingly, so that the nominal frequency is 2000Hz.  Can you try that and let us know if that reduces or eliminates the errors? 

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