Category: Hardware
Product Number: ADXL372
The latest ADXL372 datasheet (revision C) mentions a FIFO misalignment work around involving sample triggering andA the INT2 pin.
Based on the root cause explanation given in this document
Has it been considered, and would it be possible, to use the external clock feature on the INT1 pin, with appropriate phasing to the SPI clock, to avoid indeterminate synchronization delay, thus avoiding the misalignment problem completely?
