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ADIS16500 DR output and data read timing

Category: Datasheet/Specs
Product Number: ADIS16500

(1) Does the /CS pin need to be High/Open to start DR output?

The datasheet states that the DR signal is output after the START-UP TIME after the ADIS16500 is powered on. (Figure 29)
When I looked at the waveform on the oscilloscope, when I turned on the ADIS16500,
 ・/CS Low => DR signal output does not start
 ・/CS High or Open => DR signal output starts
You can see the above phenomenon.

According to the specifications of the ADIS16500, is it true that DR output will not start unless /CS is High/Open when the power is turned on?
(If possible, could you confirm the reason?)


(2) Is it okay to write/read registers while DR is inactive?

It states that you should read the Gyro and Accel registers while DR is Active.
Non-measured registers such as Product No. and MSC_CTRL
Does DR need to be Active even when writing or reading?


We apologize for the inconvenience, but thank you for your kind support.

  • Hello,

    (1) Yes, the CS line must be high for the ADIS1650x to complete its initialization sequence and begin sampling. Part of the initialization sequence is configuring the module SPI interface for proper operation, which requires the chip select to be high (SPI not selected). This stage of the initialization will not complete until CS is brought high.

    (2) Yes, writing registers while data ready is inactive is fine, just ensure that you wait for the appropriate stall time before issuing another write. Note, these writes must occur after the initialize sequence has completed, and data ready has started toggling. SPI transactions during the initialization sequence are not processed. Data ready is only relevant when reading output data registers, to ensure that all register data is sourced coherently from a single sample.

    Generally speaking, I would recommend reading back the value of any register written to verify the configuration setting has applied correctly.

    Regards,

    Alex Nolan