I am FAE in Japanese distributor.
Our customer use ADXL362.
ODR of ADXL362 is 12.5Hz and FIFO is assigned 125bits.
INT1 is assigned Water Mark Bit (Register 0x2A=0x04).
The following picture shows 11.8 seconds of INT1 "L" period.
It only takes 10s(125x1/12.5) to write 125bits FIFO.
How many cycles does it take to start writing to next FIFO after clearing INT1("H " to "L")?
How many cycles does it take to assert INT1("L" to "H") after finishing to write 125bits FIFO?
Is there a possibility that the above time will change by about 1 second?
ADX to change ADXL362
[edited by: NKokubo131 at 1:52 AM (GMT -4) on 28 Oct 2020]