I am FAE in Japanese distributor.
Our customer use ADXL362.
ODR of ADXL362 is 12.5Hz and FIFO is assigned 125bits.
INT1 is assigned Water Mark Bit (Register 0x2A=0x04).
The following picture shows 11.8 seconds of INT1 "L" period.
It only takes 10s(125x1/12.5) to write 125bits FIFO.
How many cycles does it take to start writing to next FIFO after clearing INT1("H " to "L")?
How many cycles does it take to assert INT1("L" to "H") after finishing to write 125bits FIFO?
Is there a possibility that the above time will change by about 1 second?
Hi John san
Thank you. I understand you.
Could you explain what external clock frequency should they use for ODR 12.5Hz
and how should they set the Filter Control Register?
Hi NKokubo131,They may base on the datasheet for that matter:
So as you can see here, since the ADXL362 can operate with external frequencies ranging from the nominal 51.2 kHz down to 25.6 kHz, the customer…
Hi NKokubo131,Thank you for your post. The interrupt can be cleared just as the moment that you have read enough data from the FIFO buffer that interrupt conditions are no longer met (having less than 125).
Hope this helps. Best regards,John
Thank you for your reply.
I understand you.
ODR of ADXL362 is 12.5Hz and FIFO is assigned 125bits
The read time of 125bit FIFO is just 10 seconds.
But our custmer found INT1 occurrs every 11.08seconds.
Could explain the difference?
Hi NKokubo131,You should have 125 sample sets for 10 seconds of data capture. Also, the internal clock is not accurate, and a +/-15% shift would be considered normal.
So to fill a certain number of samples, the time it would take would vary too. The deviation for the customer is 10.8% which is still acceptable.
An external clock can improve clock frequency accuracy. Hope this helps!Best regards,John
So as you can see here, since the ADXL362 can operate with external frequencies ranging from the nominal 51.2 kHz down to 25.6 kHz, the customer has 2 options to achieve this. Basing on the Filter Control Register:
Set 000 on bits [2:0] on the Filter Control register and then provide a 51.2 kHz external clock. This would result to:
Option 2: Set 001 on bits [2:0] on the Filter Control register and then provide a 25.6 kHz external clock. This would then result to:
Hope this helps! Best regards,John