ADXL372 FIFO overflow bit is set most of the time

I am using ADXL372 FIFO in continuous stream mode, part settings are as below: 

ADXL_MEASURE : BANDWIDTH = 400

ADXL_TIMING : ODR = 800

FIFO_SAMPLES = 104 (Altogether 360 (X,Y and Z) including MSB in ADXL_FIFOCTL ) 

ADXL_FIFOCTL = ADXL_FIFOCTL_FIFO_MODE_STREAM | ADXL_FIFOCTL_FIFO_MODE_SAMPLE_MSB

ADXL_INT1_MAP = ADXL_INT1_MAP_FIFO_FULL_INT1

ADXL_POWER_CTL = ADXL_POWER_CTL_MODE_FULL_BANDWIDTH  | ADXL_POWER_CTL_FILTER_SETTLE_16

After above initialization, I get water mark interrupts which I process in an interrupt handler extracting FIFO data well before occurring next interrupt. But if check FIFO_OVR bit which is set most of time, to be specific around 8 times from 24 interrupts. It also seems periodic, first 8 samples FIFO_OVR is not set but it gets set for next 8 samples and for next 8 samples its not set. This is repeated all the time. 

Also, I am expecting interrupt to be occuring at 150ms but it seems to occurs at 160ms

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    •  Analog Employees 
    on Feb 28, 2020 12:41 AM

    Thanks for the question. FIFO_Full is triggered once the actual number of samples in the FIFO reaches the number set in the FIFO_SAMPLES register. The FIFO_OVR is set whenever the FIFO is filled up. Anytime the sample size is less than 512, that bit will be off.

    The internal clock on this product has +/-15% variation which will affect the ODR speed and interrupt interval you've observed.