Datasheet lacks block schematic describing the function of ODR and BW for use of EXT_CLK and text description on page 24 don't clarify all my questions. I have EXT_CLK with 614.4 and 460.8 kHz and I am wondering which ODR I can create out of it.
My understanding is that ODR select the time base 307.2 kHz (ODR<=3200 Hz) / 614.4 kHz (ODR=6400 Hz) and BW is just a divider (/2,/4,/8,/16,/32).
Assuming that, ODR will be constantly set to ODR = 6400 Hz setting and I will be able to divide by BW and create following combinations:
EXT_CLK 614.4 kHz, BW Setting: 3200, 1600, 800, 400, 200 Hz
EXT_CLK 460.8 kHz, BW Setting: 2400, 1200, 600, 300, 150 Hz
Are my assumptions correct?
Thanks for the question. The internal 614.4KHz oscillator frequency is used exclusively for the 6400Hz ODR because it entails substantially increased power. So when replaced by an external clock much greater than 307.2kHz, please only select 6400Hz ODR option. In this case, 614.4kHz clock will provide ODR @6400Hz while 460.8kHz clock outputs data @4800Hz. For external clock <= 307.2kHz, you can select ODR <= 3200Hz where the actual ODR will scale down ratiomatrically based on the actual external clock speed. And you are right, BW is always a divider from the actual ODR.
jwang said:And you are right, BW is always a divider from the actual ODR.
For EXT_CLK=1 (614.4 & 460.8kHz) I set ODR to 0b100 (6400Hz), however any setting made in BANDWIDTH (MEASURE[0:3]) produce the same output - ODR @6400 & @4800Hz. Can you please elaborate what the BANDWIDTH does when EXT_CLK is used?
From my readings it's not working as a divider from the actual ODR...
Bandwidth can be set independently with the ODR(with a max limit at ODR/2). Change of the bandwidth should change the architecture of the front end AAF but not affect the actual output data rate. Would you elaborate on how you test the bandwidth on your side? Which might be helpful.
I used routine that I normally use for collecting data from ADXL372 FIFO to SRAM. This function is just minimally edited:1. I set while() to collect constant amount of data (6400 samples) and report (timestamp-stop) once done.2. I removed any other way to exit the loop (on STATUS.FIFO_OVR & STATUS1.INACT)3. I removed waiting for activity event so the part start measuring right away (timestamp-start).4. And out of paranoia, I set INACT_COUNT=0XFF00; And these are the results T=(timestamp_stop - timestamp_start):
FIFO fills with the measurement data regardless the BW setting...
BW setting sets the anti-aliasing circuity in front of ADC which doesn't change the ADC sampling rate, but ODR setting does.