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ADXL372 EXT_CLOCK: spurious samples

Our product has 3 ADXL372 accelerometers and for the last few months we've had them connected to a development board, configured to use the EXT_CLOCK that is being generated at 307.2kHz from a CPU pin.  This has been working well.  Using the EXT_CLOCK pin allows us to keep all three accelerometers synchronised.  (We know EXT_SYNC is unreliable, hence avoid it, see https://ez.analog.com/mems/f/q-a/110729/adxl372-ext_sync-how-to-keep-3-accelerometers-in-sync )
 
Our first real prototype used a LTC6906 with a set resistor to adjust the clock to 307kHz.  In this configuration we would see a spurious acceleration of almost maximum g, usually just on one channel but sometimes on more.  This would usually occur every 10 seconds, more or less.  Eg, here's a one channel example (this is the raw reading from the accelerometer):
Y axis, 800Hz ODR
-5
0
1
2
-3
-1
1
0
2
2
0
2
2
0
2
1
1022
-14
-16
-11
-17
-14
-19
-12
-11
-14
-14
-11
-14
-11
-14
-14
-13
-11
-13
-13
-10
-13
-11
-15
-11
-11
-9
 
We had some other problems with the first prototype, so have quickly moved on to version 2, this time using a SiT1569 at 390kHz.  As this is above the 307.2kHz default, we have set the accelerometers to run at 6400Hz ODR to permit an EXT_CLOCK of max 614kHz.
 
However, we get immediate bad readings.  Either constant zeros, spurious signals or FIFO misalignment.  If we switch the accelerometer to use it's internal clock the problem readings immediately go away, although I did see some FIFO misalignment.
 
I should finally add that we have been unable to detect any obvious difference in signal quality of the EXT_CLOCK between the working dev board the 2 prototype boards.  The clock signals look nice and square, rail to rail.  But maybe our oscilloscope isn't showing the whole story.
 
So we would like to know how to get the ADXL372 to use the EXT_CLOCK signal reliably.  Is there any optimum settings, sample rate, signal conditioning or anything else that will make it robust?  Or is the EXT_CLOCK known to sometimes be problematic?
Thanks!
Parents
  • Hi jwang,

    The problem is very, very hard to pin down.  On my dev board the accelerometers are failing instantly, yet on production boards they _seem_ to be working.  However we are in the process of adding debugging to our production boards because we can't see the signals so they may be failing and recovering without us knowing.  Sorry for being so vague!

    However, you asked for a schematic and here it is:

    And for a waveform capture (but this is the SiT1569).  Note this capture has "persistence" turned on which is why it looks so fat:

    Yes I did try at 3200Hz and lower ones too.  None helped.

    As you may know I've another open ticket https://ez.analog.com/mems/f/q-a/116556/adxl372-ext_clock-at-above-307-2khz-seems-to-cause-extra-readings/347849 sort-of related to this issue and our current thinking is to switch all three accelerometers to use their internal clocks.  But this means they won't be synchronised so could prove to be a problem for our product.  To understand if this is the right thing to do, we really just need to know if EXT_CLOCK _may_ be known to sometimes be unreliable and if INT_CLOCK is the only way to be sure of never getting a spurious trigger or missed sample.

    Thanks for your help!

  • Hi jwang,

    We're under pressure to deliver reliable readings so are currently working on a driver that will synchronise the accelerometers when they're using their internal clocks as we presume the external clock will continue to have issues.  One outcome of the incomplete driver is this rather unscientific observation:

    After leaving my Dev board in active mode for a while, here are the error totals (where an error is a flatline (accelerometer axis typically goes to 0) or FIFO misalignment (bit 1 incorrect for an axis):
    Acc1Errors = 223
    Acc2Errors = 124
    Acc0Errors = 56
    This is using the 390kHz External Clock with ODR set to 800Hz.

    What's interesting, is the speed of each accelerometer's internal clock (I measure this when I switch to the internal clock, same board, same accelerometers):
    ACC:1 Freq=840.776
    ACC:2 Freq=818.043
    ACC:0 Freq=777.172

    Is it a coincidence that the faster the internal clock is, the more errors it has?

    And FWIW, after 4 hours running on their internal clocks, I've had no errors from any of the accelerometers.  This isn't an exhaustive test, but so far it's looking promising.

Reply
  • Hi jwang,

    We're under pressure to deliver reliable readings so are currently working on a driver that will synchronise the accelerometers when they're using their internal clocks as we presume the external clock will continue to have issues.  One outcome of the incomplete driver is this rather unscientific observation:

    After leaving my Dev board in active mode for a while, here are the error totals (where an error is a flatline (accelerometer axis typically goes to 0) or FIFO misalignment (bit 1 incorrect for an axis):
    Acc1Errors = 223
    Acc2Errors = 124
    Acc0Errors = 56
    This is using the 390kHz External Clock with ODR set to 800Hz.

    What's interesting, is the speed of each accelerometer's internal clock (I measure this when I switch to the internal clock, same board, same accelerometers):
    ACC:1 Freq=840.776
    ACC:2 Freq=818.043
    ACC:0 Freq=777.172

    Is it a coincidence that the faster the internal clock is, the more errors it has?

    And FWIW, after 4 hours running on their internal clocks, I've had no errors from any of the accelerometers.  This isn't an exhaustive test, but so far it's looking promising.

Children
  • Thanks for the update, and it's good to hear so far so good by using the internal clock. We don't have enough characterization data yet to show the correlation between the internal clock speed and the number of errors that might occur but this is an interesting point to look into. The product line is currently working on the issue and will definitely take this into consideration.