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ADXL372 EXT_CLOCK: spurious samples

Our product has 3 ADXL372 accelerometers and for the last few months we've had them connected to a development board, configured to use the EXT_CLOCK that is being generated at 307.2kHz from a CPU pin.  This has been working well.  Using the EXT_CLOCK pin allows us to keep all three accelerometers synchronised.  (We know EXT_SYNC is unreliable, hence avoid it, see https://ez.analog.com/mems/f/q-a/110729/adxl372-ext_sync-how-to-keep-3-accelerometers-in-sync )
 
Our first real prototype used a LTC6906 with a set resistor to adjust the clock to 307kHz.  In this configuration we would see a spurious acceleration of almost maximum g, usually just on one channel but sometimes on more.  This would usually occur every 10 seconds, more or less.  Eg, here's a one channel example (this is the raw reading from the accelerometer):
Y axis, 800Hz ODR
-5
0
1
2
-3
-1
1
0
2
2
0
2
2
0
2
1
1022
-14
-16
-11
-17
-14
-19
-12
-11
-14
-14
-11
-14
-11
-14
-14
-13
-11
-13
-13
-10
-13
-11
-15
-11
-11
-9
 
We had some other problems with the first prototype, so have quickly moved on to version 2, this time using a SiT1569 at 390kHz.  As this is above the 307.2kHz default, we have set the accelerometers to run at 6400Hz ODR to permit an EXT_CLOCK of max 614kHz.
 
However, we get immediate bad readings.  Either constant zeros, spurious signals or FIFO misalignment.  If we switch the accelerometer to use it's internal clock the problem readings immediately go away, although I did see some FIFO misalignment.
 
I should finally add that we have been unable to detect any obvious difference in signal quality of the EXT_CLOCK between the working dev board the 2 prototype boards.  The clock signals look nice and square, rail to rail.  But maybe our oscilloscope isn't showing the whole story.
 
So we would like to know how to get the ADXL372 to use the EXT_CLOCK signal reliably.  Is there any optimum settings, sample rate, signal conditioning or anything else that will make it robust?  Or is the EXT_CLOCK known to sometimes be problematic?
Thanks!
Parents
  • Hi jwang,

    The problem is very, very hard to pin down.  On my dev board the accelerometers are failing instantly, yet on production boards they _seem_ to be working.  However we are in the process of adding debugging to our production boards because we can't see the signals so they may be failing and recovering without us knowing.  Sorry for being so vague!

    However, you asked for a schematic and here it is:

    And for a waveform capture (but this is the SiT1569).  Note this capture has "persistence" turned on which is why it looks so fat:

    Yes I did try at 3200Hz and lower ones too.  None helped.

    As you may know I've another open ticket https://ez.analog.com/mems/f/q-a/116556/adxl372-ext_clock-at-above-307-2khz-seems-to-cause-extra-readings/347849 sort-of related to this issue and our current thinking is to switch all three accelerometers to use their internal clocks.  But this means they won't be synchronised so could prove to be a problem for our product.  To understand if this is the right thing to do, we really just need to know if EXT_CLOCK _may_ be known to sometimes be unreliable and if INT_CLOCK is the only way to be sure of never getting a spurious trigger or missed sample.

    Thanks for your help!

  • I can't find any remaining boards with the LTC6906, I'll have another search but we did have a long hard look at the signal from that part on a CRO and didn't see anything unusual.  It just looked like a reasonable rail to rail square wave.

    The behaviour and rate at which errors are occurring varies wildly.  My comment about "every 10 seconds" was just on one board that we since modified to try to isolate this issue.

    I will try to let the FIFO fill with 170 samples instead of 68 and report.  But there is a chance the CPU will not service the in time FIFO causing it to overflow.

    Note however we have now decided our next design will remove the EXT_CLOCK and revert to using the ADXL372 internal clock in the hope we don't get spurious triggers, flatlines & missing samples.  We will try to compensate for the lack of synchronisation by timestamping the time at which the FIFO Watermark interrupt occurs from each accelerometer.  Please let us know if there are any known problems using the internal clock before we commit to the new design.

    As a side note, we are currently trying to overcome the errors caused by the delay in sampling each axis - the ADXL372 internal MUX switching time means each axis is not synchronised hence our calculations incur errors.  I'll quickly ask if you know what the switching time is (we think it's linked to the ODR, so switching time varies as the ODR is varied).

Reply
  • I can't find any remaining boards with the LTC6906, I'll have another search but we did have a long hard look at the signal from that part on a CRO and didn't see anything unusual.  It just looked like a reasonable rail to rail square wave.

    The behaviour and rate at which errors are occurring varies wildly.  My comment about "every 10 seconds" was just on one board that we since modified to try to isolate this issue.

    I will try to let the FIFO fill with 170 samples instead of 68 and report.  But there is a chance the CPU will not service the in time FIFO causing it to overflow.

    Note however we have now decided our next design will remove the EXT_CLOCK and revert to using the ADXL372 internal clock in the hope we don't get spurious triggers, flatlines & missing samples.  We will try to compensate for the lack of synchronisation by timestamping the time at which the FIFO Watermark interrupt occurs from each accelerometer.  Please let us know if there are any known problems using the internal clock before we commit to the new design.

    As a side note, we are currently trying to overcome the errors caused by the delay in sampling each axis - the ADXL372 internal MUX switching time means each axis is not synchronised hence our calculations incur errors.  I'll quickly ask if you know what the switching time is (we think it's linked to the ODR, so switching time varies as the ODR is varied).

Children
  • Hi Richard,

    There shouldn't be spurious triggers using the internal clock, though I have to say that I still recommend setting the FIFO Sample size to greater than 500 @ 3200/6400Hz ODR to avoid the chances of missing samples. We're investigating the issues at the moment together with the external clock/sync issue, will let you know once we have an update.

    Regarding the delay in sampling each axis, it's about 104us in between two consecutive access.

    I hope this helps.

  • Hi JWang,

    I'd like to try your recommendation, so can I asked specifically what I should do?

    I'm reading triplets (XYZ), currently my watermark is set to 68 * 3 = 204.  When the FIFO WM interrupt occurs I read 64 * 3 = 192 bytes.

    If you believe the FIFO should fill to 500 bytes, then shall I set the FIFO WM to 167 * 3 = 501 and do I still read 64 * 3 = 192 bytes or do I read 166 * 3 = 498 bytes?  (I say 166 because we're supposed to leave at least 1 triplet in the FIFO to avoid misalignment).

    Thanks!

  • Hi JWang,

    BTW, thanks very much for citing the switching time - it's very very helpful for us to know this to compensate for errors when calculating direction of sudden impacts.  And If I can hijack this thread with one more related question --- what's the sampling order?  We're not exactly sure, but we think it's Y->X->Z, could you please confirm?

    Thanks!

  • Say you have FIFO Watermark set to 501, as soon as interrupt triggers, you can pull all the 501 samples out at once, which are 167 sets of samples in total. You don't have to leave one sample sets unless you are using the full FIFO sample size, 510 when 3 axes are enabled in this case. I hope this helps.

  • The sensor samples in the order of X-> Y-> Z. Can you inform why you think it would be Y-> X -> Z? 

  • One more info to add, it takes about 50us between the finish of Z-axis data conversion, to the trigger of Data Ready interrupt. This may be also useful to your application.

  • Hi jwang,

    Ah, the sampling order was an educated guess from our math boffin, but based on your answer he's changed his mind and agrees with you Slight smile.  Thank you very much for these details, it really is a big help!