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ADXL372 EXT_SYNC : how to keep 3 accelerometers in sync?

Our product is using 3 * ADXL372 accelerometers.  It's important that all 3 accelerometers be synchronised.  To achieve this we have been focused on using the EXT_SYNC feature.  We are also trying to save power, so have been using the FIFO to buffer 68 XYZ samples and using the INT FULL signal from one of the accelerometers as a CPU trigger to read 64 samples (making sure we leave some samples in the FIFO as the datasheet suggests).

We have connected the CS signals from the 3 accelerometers to the same CPU port so all 3 lines can switch at exactly the same time when we send initialisation commands to them.
The first issue we found was each accelerometer would begin buffer to its FIFO at different times.

INT0 is routed to the CPU, INT1 & INT2 we're just monitoring on the logic analyser.  This is the first trigger after measurement start.  As you can see, each ADXL372 signals FIFO_FULL at different times.  In the left trace the FILTER_SETTLING time is 370ms, but in the right trace it's 10ms.  So the right trace is much better, but still not perfect.

Our solution is to do this:

  • Initialise (FIFO mode, INT source, etc).  Set FIFO threshold to 3 * 32 samples.
  • Start sampling & await INT
  • On INT, stop the EXT_SYNC clock
  • For each chip, read the number of samples in the FIFO and read out all except the last sample triplet (so there's one XYZ triplet left in each FIFO)
  • Adjust the FIFO threshold up to 3 * 68 samples and resume the EXT_SYNC clock

This is what the signal now looks like (the bottom 3 signals are the FIFO FULL INT lines):

So, that's the background.  We now seem to have all three accelerometers in synch.  However our problem is that a few 10s of seconds after this, it looks like an accelerometer misses samples:

On the left all INT lines activate at the same time meaning all FIFO's have reached the threshold at the same time - perfect!  However, 64 samples later we see INT1 & INT2 both activate in unison, but INT0 takes an extra 4 sample clocks.  So ADXL372 # 0 is now behind and the FIFOs are now out of synch - NG!

In this trace, the EXT_SYNC is 1024Hz.  The TIMING.ODR field is set to 6400Hz.

Are we doing something wrong?

What must we do to ensure all accelerometers remain in synch?