I working CAD about ADXL355
ADXL355 has DETAIL MARK
1 is this mark connected to any terminals?
2 Are VIA and GND Plane prohibited around this Mark?
Firstly, it would be good if AD could recommend the best practice for PCB layouts for the ADXL355. I am always interested in PCB layout recommendations from AD for their chips.
Now what I do
I understand that “Detail A” is not connected, it is just a visual mark. All my chips are now soldered down and there is no other mention of “Detail A” anywhere, so I cannot confirm this at the moment.
I would avoid vias under the chip as this could add noise, depending on the via type.
I like to have a square ground plane directly under the chip with a solder resist layer on top of that ground plane.
There is a good write up on ground planes but this is more for high performance ADC.
Not fully needed for the ADXL355 but good practice anyhow.
So to answer your questions
1) I am pretty sure this is just a visual mark and has no electrical contacts but it would be good to get confirmation from AD
2) No restriction except be careful of via as they can add noise. Ground plane under the chip is what I always like to do. Again it would be good to get confirmation from AD.