I have same questions about EXT_SYNC=01 Mode of ADXL355.
Could you please advise me timing specification about the external sync signal? Are there any constraint about the sync signal?
According to the datasheet of ADXL355, EXT_SYNC=01 mode can be used with only a single sync pulse. Can we send only one
sync pulse for synchronization in this case? Or should we send sync pulse continuously?
I have the same question,
but additionally, when the external CLK is used, and if there is possibility to send only one external sync pulse to the 14th pin (DRDY),
is it possible somehow to reassign this pin to get DRDY pulses after the single SYNC pulse? If yes - how?
Now I have some number of PCBs, where pin 12 (Int1) is not connected, so I can't remap DataReady Int to Int1
and pins 13 &14 are busy with CLK and SYNC.
Also it would be good to see time chart for sync mode:
External CLK chart,
External Sync chart,
Data Ready state chart (Is data ready after each 1024 ext_clk pulses since External Sync? Where is the better time interval for data reading to minimize the SPI/I2C activity influence to ADXL355' ADC convesion?)
I guess if we have to send multiple sync pulses, we need to align them with the decimation filters which is a tedious task. Hence they recommend to use a single pulse but this will definitely lead to drifting of clocks after a certain time.
Also when you enabled EXT_SYNC=01 mode, did you also assign EXT_CLK = 1 and set the DRDY_OFF bit of the Power Control Register? Is the EXT_CLK always 1.024MHz irrespective of the required Output Data Rate?
swar said:Hence they recommend to use a single pulse but this will definitely lead to drifting of clocks after a certain time.
My interest is to use one high stable EXTERNAL CLK source for a number of ADXL355, no internal CLK at all. So, I don't expect any drift and additionaly use the EXTERNAL CLK as real time clock.
In the Datasheet for ADXL354/355 the table 46 on the page 38 the next comment is placed for EXT_SYNC=01 mode:
"External sync, no interpolation filter. After synchronization, and for EXT_SYNC within specification, DATA_RDY occurs on EXT_SYNC."
Is it mean, that after one sync pulse one may get Data_Rdy pulses?