Hello,I have recently purchased a breakout board of the ADIS16470 (ADIS16470/PCBZ). I tested it with a discovery board (through the SPI port) and I had an issue. I attach an image of the oscilloscope used on the test.- In yellow (1st channel) -> Clock- In Blue (2nd channel) -> DIN (MISO)- In purple (3rd channel) -> DOUT (MOSI)The circles highlighted the SPI transaction.In order to get a correct response, I had to send 32-bit clock pulse instead of a 16-bit one (I have to wait 32 instead of 16).I have asked for the PROD_ID (0x72) (1_petition image). As in the datasheet Figure 28 example.
On the other hand, I have also asked for the PROD_ID (0x72) 3 times (3_petition image) consecutively. In this case, the first response takes 8 clock cycles (this is not ok, isn't it?), an then the other ones arrive "together", without any gap.
Am I doing anything wrong? Is this supossed to happen?
Thank you for making these adjustments. I would probably try the following, next:
1. Add a CS high time, between each 16-bit segment. I would be surprised if this is the problem, but it is easy to try…
Thank you for your interest in this product and for posting this question! I suspect that the primary issue could be a violation of the read stall time. See Table 2 and Figure 4 in the ADIS16470 datasheet and let me know what you think.
https://www.analog.com/media/en/technical-documentation/data-sheets/adis16470.pdf#page=05
We began (meeting the specified protocol of course), by testing if the problem were one of those (both times), and we did not succeed neither.
I will try to post the oscilloscope images of those tests tomorrow.
Thank you! I understand that this can be frustrating, but I can assure you that the protocol in the datasheet represents how we test these devices in practice and how many others are using them. The only other thing that I would wonder about is the chip select line. It wasn't shown in the scope plots so I wasn't able to review its timing. I will be travelling the rest of the week, so apologies if my future replies are delayed.
thank you very much. Yes, of course I understand, and I know that the protocol is for sure working. I did my question wrong, definitely. The appropiated question should be "what am I doing wrong?".
The images:
T_stall
T_readrate
every 1ms.