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ADXL372 FIFO data error with long time reading


I am using the adxl372 to measure the x,y,z acc data, the initialization is normal.

and i get the data through the FIFO, here comes the problem.

I set FIFO samples num as 480 (0xE0,160 samples for each axis),set the watermark interrupt, in the interrupt callback function,

I read the FIFO data through SPI.(read 157 samples each time)

Everything is fine in the begining, but a little moment later, the data goes wrong, and then three axes data begin to swap. 

As the picture shows below,

I don't know why this comes like this, the data swaps every time i read the fifo(157 samples).

Best regards.

  • I am experiencing the same problem for sampling rates above 3200 Hz, with and without EXT_CLK (<= 3200 Hz works perfectly fine). In short, the series start indicator moves from X axis to another one as shown on picture below. I check all STATUS register flags before read and I control that at least one sample set (6 bytes for XYZ) remains in a FIFO after read. I do 960 multi-byte read on watermark, FIFO_SAMPLES=0x01E3, so 160 XYZ concurrent samples are read all at once. The FIFO is in a stream mode, package marking code "372B 1904 3263" (space=new line).

    Did anyone found out what might be the cause?

  • Thanks for the question. It looks like this is some timing-related issue with the internal FIFO architecture and we are currently investigating the potential root cause. In the meantime, I'd suggest to stream from data register to avoid this data misalignment issue.

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  • Hi jwang, thank you for looking into this. I have some more inputs that might help.

    In order to investigate the issue, we have started to read the STATUS, STATUS2 and FIFO_ENTRIES register always before and also after reading the FIFO_DATA register. We have found, that while we always get enough FIFO_ENTRIES (0x01E3) prior the multibyte-read of 960B from FIFO_DATA register, sometimes we get unexpected FIFO_ENTRIES after pulling FIFO_DATA. To explain, when it works (series bit correctly set), we get expected following readings from the FIFO_ENTRIES right after we pull the FIFO_DATA:

    ODR [Hz] / FIFO_ENTRIES [dec]: 400/15, 800/27, 1600/54, 3200/107, 6400/226

    However, when the FIFO series bit gets misaligned, the FIFO_ENTRIES returns 0 samples (after constant 960B FIFO_DATA read). I guess this explains the data misalignment as there are no valid data left in the FIFO. However, we don't know why this happens as there are certainly enough entries prior the read and therefore should be also enough after the read. I have tried different variations - 1) keep FIFO_SAMPLES = 0x01E3 and pull just 240B from FIFO_DATA; 2) lower FIFO_SAMPLES to 0x0078 and read just 199B from FIFO_DATA, but nothing helped to resolve this problem.

    We are now planning to buy a SPI logic analyser to see what's happening on SPI and power lines when this happens. To me it seems that either we are somewhat pulling more data from the FIFO when this happens or the ADXL372 dis-validate or forgets it's own FIFO_ENTRIES. This happens in about every third measurement on 6400 Hz we do, there are measurements where everything seems nominal.

  • Hi

    I was wondering if there was any update regarding this? I've recently noticed one of the devices that contain the ADXL372 exhibits the same issue with FIFO axis swapping during some reads with a watermark of 160 values (Data is completely swapped or we get random spikes). Is there a workaround to continue using the FIFO? If I do a single read from the FIFO (When it's set in-stream mode) for the total amount of data I want (640 Samples), will the FIFO keep popping data and adding new data to it?

    I've previously tried to read the XYZ register but had overhead issues causing delays in the data collection when the ODR is set a 6400Hz. If the FIFO is unsuitable is there a way to sample the data from the XYZ registers at 6400Hz?