Post Go back to editing

ADF7021BCPZ-RL Test DAC Method

Hello experts,

I want to use the Test DAC feature on ADF7021BCPZ-RL. I followed the instructions on AN-852 Application Notes and referred to ADF7021 data sheet stating that "The output can be viewed on the SWD pin. This signal, when filtered appropriately, can then be used to do ... etc"

I haven't succeeded so far, please help.

Appreciate your help so much, best regards,


  • Hi Bud_Nug,

    Are you using the SWD pin as the output? Also, can you specify the value you have used for Register 14? 

    Thank you very much.



  • Hello Dvalles,

    Thank you for your response, appreciate it so much,

    1. Yes, the output monitored at SWD Pin
    2. Register 14 filled with 0x1E
    3. Register 12 filled with 0x14C (threshold free running, swd pin high after next syncword, data length 1)

    Thank you very much, stay healthy, best regards,

    Bud_Nug & team

  • Dear dValles & other experts here,

    My best regards and appreciation for your response to my problem here.

    Here is the additional information about my team's work regarding ADF7021:

    We use ADF7021 to design a VHF radio working on 82-86 MHz, currently we are testing the design @ 84 MHz. With external LNA we've achieved -106 dBm Rx sensitivity test over cable + attenuator transmission. Sure this result is below ADF7021 capability I believe, but it,s quite acceptable for our requirement.

    The issue rises when we test the design over the air using the designated antenna, we found that noise/interference on the test site was measured as high as -86 dBm/1kHz_BW. So we were back to the lab and test the design using noise generator and we found that our design has a 20 dB SNR requirement to be error free.

    After tweaking the loop filter and VCO parameter we could lower the SNR requirement to 14 dB. It looks like a significant improvement we had, but still far from acceptable compared with other radio on the market which could achieve 6 dB SNR to be error free :(

    That is the reason we are desperately want to see the demodulated signal eye pattern using the Test DAC feature.

    I have the documents listed below, and I still feel lack of information about ADF7021's test modes :(

    * AN-915:
    CDR Operation for ADF7020, ADF7020-1, ADF7021, and ADF7025

    * AN-859:
    RF Port Impedance Data, Matching, and External Component Selection for the ADF7020-1, ADF7021, and ADF7021-N

    * ADF7021 Data Sheet

    * ADF7021-V Data Sheet

    * AN-764:
    ADF7020 RF Port Impedance Values for Matching Purposes

    * AN-1182:
    Understanding and Optimizing the AFC Loop on the ADF7021 for Minimum Preamble

    * ADF7021DBXEvalNote.pdf:
    Evaluation Boards for ADF7021 ISM Band Transceiver EVAL-ADF7021DBZX

    * adf7021-v_eval_note_sch_bom.pdf:
    Evaluation Boards for ADF7021-V Narrow-Band Transceiver EVAL-ADF7021-VDBxZ

    * ADF7021-Silicon Anomaly Sheet-15238.pdf

    We also found a thesis describing the measurement of eye diagram on ADF7021, but it is not disclosure the parameters used in performing it:

    * 08-09_Mahy.pdf:
    Design and Implementation of
    On-board Telecommunication
    System of Student Nanosatellite
    OUFTI-1 of University of Liege
    by Francois Mahy

    "The eye diagram for the ADF7021 is complicated to have because we cannot directly obtain it like in a classical FM demodulator. In the ADF7021, the eye diagram is the result of an analog-to-digital converter (ADC) that samples the signal at IF. Then, the diagram contains a high quantisation noise. Moreover the gain of the ADC has to be adjusted. If this gain is not exactly correct, none of diagram appears. This gain changes with the baudrate and is not really calculable.

    In order to see an eye diagram from the ADF7021, we had to program it to provide the output of the ADC on the SWD pin. An appropriated filter has to be placed at the SWD pin to reconstruct the signal. This filter depends upon the baudrate of the incoming signal. All these parameters make the eye diagram difficult to have. It was so difficult to know if it was the eye diagram parameters, the programmed frequency of something else that is wrong if none of eye diagram appears."

    Would you please provide the missing document for us regarding the test modes available on ADF7021.

    We appreciate your help and sharing very much

    Thank you, stay healthy, best regards,

    Bud_Nug & team

  • Hi Bud_Nug & team,

    Sorry for the late reply.

    The documents related to the ADF7021 can be found on this link: ADF7021-N Datasheet and Product Info | Analog Devices, which you already have.

    The register values (specifically Reg14) you provided is enough to produce an output on the SWD pin, however, the raw data is not enough to get the eye diagram.

    From  ADF7021DBXEvalNote (Test DAC Output page 9), the RC filter is necessary to properly use the output of the SWD pin. You can design an RC (easier to use LPF) filter that will fit your application's data rate, you can also try to change the component values of the given RC filter connections using software that is available to you.