Why do  interrupts  in the interrupt_source_1 register assert even if they are not enabled via the corresponding interrupt mask register?

I have observed that the interrupt_source_1 interrupts assert (in the source register, not on the hardware interrupt line) when ever an interrupt condition occurs even though they are not enabled in the corresponding interrupt_mask_1 register? Why is this?

  • The interrupts in the interrupt_source_1 register are always active as interrupt sources in the interrupt_source_1 register independent of the interrupt_mask_1 setting. To mirror these interrupts to the hardware interrupt pin (IRQ_GP3), and the ADF7024 status word, the corresponding interrupt bit in the register interrupt_mask_1 should be set to Logic 1.

    Note that the interrupts in the interrupt_source_0 register behave differently and need to be enabled in the interrupt_mask_0 register to make them active as interrupt sources in the interrupt_source_0 register. Enabling an interrupt in the interrupt_source_0 register also mirrors the interrupt to the IRQ_GP3 pin and the ADF7024 status word.

  • This question has been closed by the EZ team and is assumed answered.