Hi, I am working on AD9081 with ZCU 102. I am using (TX: JESD 6 mode and RX: JESD 16 mode) configuration. When I send the data, I am concatenating the same 16-bit data and sending as 32-bit to TX TPL core input. RX TPL core output is also 32-bit in my design but I am taking only half of the output data because it is concatenated. What is the effect of using first 16-bit of the TPL core output size to my design. Also could I decrease the TPL core input and output sizes without affecting the bandwidth because my modulator and demodulator have 16-bit inputs and outputs. Is this approach feasible? Any help will be appreciated.
edited title with product name.
[edited by: Dorant at 2:37 PM (GMT -5) on 16 Jan 2023]