I have the following query:
We have 2 ADF7242 Eval Boards with input and output connected via SMA Cables using proper attenuators.
While the two boards are communicating with each other, we suspect that the retries are not happening when there is reception/acknowledgement failure.
We tried to following setup to understand the operation
At the transmitter side we have compiled following test cases with CSMA/CA enabled: a)We enabled auto_ack , cca retries set to 7 and frame_retries set to 5. b)We enabled auto_ack , cca retries set to 4 and frame_retries set to 3.
Our test case is as follows:
1) We have switched the receiver off in order to get no acknowledgements.
We are expecting to see the transmitter retry each packet multiple times in this configuration. Is this correct ?
Is there anyway to turn on a debug log to see if the retry is actually happening ?
We expect the time stamp between the consecutive packets was expected to have a delay of: a) (864us+192us)*5 (no. of retries)--for case a above b) (864us+192us)*3 (no. of retries)---for case b above
Is our understanding correct ?
The actual results show the drive responding in 20 to 35 micro seconds in both cases. We expected the time difference should have been more as retries should have been triggered as the receiver is off (no ack).
The easiest way to determine if the desired state transitions are occurring would be to measure the current drawn by the part vs time. for example a differential oscilloscope probe across a 10 Ohm resistor on the supply (or using the math function to subtract the voltage measured by a standard probe on one side of the resistor from the voltage measured by 2nd standard probe on the other side)
The current will show which state the part is in (per the datasheet current numbers)