Connect IIO to ADC-SOC Cyclone 5 Cortex A9

Hi,

i am using the terasic ADC-SOC for evaluation purpose. The ADC-SOC generates data using two 125 MSpS AD9254.

Terasic provides a very basic example on how to get data out of the ADC into the HPS (Cortex A9) and print them out on linux running on the HPS (Cortex A9).

I've seen the IIO Oscilloscope project, which is quite awesome. I have some questions:

- How to connect Evaluation boards to the software? How is the data path, I mean how is the software getting the input data?

- Is it possible to run on the HPS of the Cyclone 5 of my ADC-SOC? I can pass the data to the linux and can grab it with C code. How to push it to IIO or am I understand it wrong?

Thanks for your response

Nils

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  • Hi Michael,

    after reading more docs, I think i understand it a bit better, but maybe you can advise me a bit.

    IIO and libio are only a linux thing and doesn't depend on the FPGA correct? And it is working remote via ethernet and usb and direct on the Hardware correct?

    So I am especially interested in getting the data from an Altera FPGA (Cyclone V or Arria 10) via JESD204b from an ADC (AD9860/AD9234), buffer it and transfer it to the linux running on the internal HPS (Cortex A9). How should a HDL driver look like in order to connect the FPGA data to libio and then use it on iio scope?

    Nils

Reply
  • Hi Michael,

    after reading more docs, I think i understand it a bit better, but maybe you can advise me a bit.

    IIO and libio are only a linux thing and doesn't depend on the FPGA correct? And it is working remote via ethernet and usb and direct on the Hardware correct?

    So I am especially interested in getting the data from an Altera FPGA (Cyclone V or Arria 10) via JESD204b from an ADC (AD9860/AD9234), buffer it and transfer it to the linux running on the internal HPS (Cortex A9). How should a HDL driver look like in order to connect the FPGA data to libio and then use it on iio scope?

    Nils

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