I'm leveraging Analog Device's reference design for the AD9361 for a design of my own on the ZC702/Zedboard. I've removed a lot of the components I don't need (HDMI, spdif, XADC, some GPIOs) from the HDL and devicetree. I'm of course still using the interface (control and DMA) to the AD9361 in my design, but I'm only using the RX capability.
I'd like to be able to reload FPGA bitstreams on the fly from the ARM. Xilinx has made this straightforward in terms of how to do it on the ARM, but when I switch bitstreams the interface to the AD9361 (specifically the ability to get IQ samples) unsurprisingly no longer works.
I realize bitstream partial reconfiguration is the proper way to do this, but creating partial reconfiguration bitstreams is a huge pain. This is probably a a loaded question, but would there be someway to '"reset" the AD9361 (or is it just the HDL logic?) via the ARM after I reload a bitstream and could then resume getting IQ samples from the RFIC?