"Resetting" AD9361 from software?

Question

I'm leveraging Analog Device's reference design for the AD9361 for a design of my own on the ZC702/Zedboard. I've removed a lot of the components I don't need (HDMI, spdif, XADC, some GPIOs) from the HDL and devicetree. I'm of course still using the interface (control and DMA) to the AD9361 in my design, but I'm only using the RX capability. 
 I'd like to be able to reload FPGA bitstreams on the fly from the ARM. Xilinx has made this straightforward in terms of how to do it on the ARM, but when I switch bitstreams the interface to the AD9361 (specifically the ability to get IQ samples) unsurprisingly no longer works. 
 I realize bitstream partial reconfiguration is the proper way to do this, but creating partial reconfiguration bitstreams is a huge pain. This is probably a a loaded question, but would there be someway to '"reset" the AD9361 (or is it just the HDL logic?) via the ARM after I reload a bitstream and could then resume getting IQ samples from the RFIC?

larsc · Accepted Answer

Hi, 
 You don't necessarily need to build the drivers as a module. You can bind/unbind a driver by writing sysfs attributes. Before loading the new bitstream you should unbind all drivers for devices that are found in the FPGA fabric and after loading the bistream bind them again. 
 For example to unbind/bind the DMA driver do the following: 
 
 echo 7c40000.dma > /sys/bus/platform/drivers/dma-axi-dmac/unbind 
 echo 7c42000.dma > /sys/bus/platform/drivers/dma-axi-dmac/unbind 
 # reload bitstream 
 echo 7c40000.dma > /sys/bus/platform/drivers/dma-axi-dmac/bind 
 echo 7c42000.dma > /sys/bus/platform/drivers/dma-axi-dmac/bind 
 
 - Lars)

njp · Answer

Thanks Lars, I'll give that a try. 
 What I did find that worked for me was loading in the following order (1. virt-dma.ko, 2. dma-axi-dmac.ko, 3. cf-axi-adc.ko, ad9361.ko) and unloading in the reverse order, excluding ad9361.ko. 
 Your way is cleaner though so I'll give that a try.

asvillamar · Answer

I found a solution that works for me on the zed board using the fmcomms2 project. For other boards it is probably a very similar process. I needed to unbind and then rebind certain drivers to re-initialize the AD9361. Here are the commands I ran: echo 79020000.cf-ad9361-lpc > /sys/bus/platform/drivers/cf_axi_adc/unbind echo 79024000.cf-ad9361-dds-core-lpc > /sys/bus/platform/drivers/cf_axi_dds/unbind echo 7c400000.dma > /sys/bus/platform/drivers/dma-axi-dmac/unbind echo 7c420000.dma > /sys/bus/platform/drivers/dma-axi-dmac/unbind # PerformFPGA update (fpgautil -b bit.bin) echo 7c400000.dma > /sys/bus/platform/drivers/dma-axi-dmac/bind echo 7c420000.dma > /sys/bus/platform/drivers/dma-axi-dmac/bind echo 79024000.cf-ad9361-dds-core-lpc > /sys/bus/platform/drivers/cf_axi_dds/bind echo 79020000.cf-ad9361-lpc > /sys/bus/platform/drivers/cf_axi_adc/bind After doing it like this I have a new FPGA image and I can continue to use the AD9361 for transmission ( i am not using for RX and have not tested). I needed to do it in this specific order to get it to work properly. I am not sure on other platforms if the exact same commands will work but the idea is similar. There might be more drivers I need to unbind and rebind in case anything else got into a bad state during FPGA update, but I will find those out soon enough.

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"Resetting" AD9361 from software?