Modification of Analog Devices' API for programming ADRV9025 on custom hardware

Please see above

Thanks Ramarao for the reply,

We have read your suggestions. We are trying to understand BBIC related parameter files.

For example, we found the following definitions:

#define BBICCOREREGPATH      "/dev/uio0\0"
#define BBICRAMPATH          "/dev/uio1\0"
#define BBICSPIADVREG_PATH   "/dev/uio2\0"

Our FPGA VHDL design is based on the ZCU102 reference design, and we would like to understand how these UIO device nodes are mapped to the FPGA hardware.

Specifically, we would like to know that How are /dev/uio0, /dev/uio1, and /dev/uio2 mapped to the corresponding FPGA IP blocks?

Regards
Mahima

Please reply

Hello mahima90 ,

I moved your thread to the Linux Software Drivers group, as this is a software related question. Someone from here might be able to help.