We are using the QuadMxFE platform with the VCU118 FPGA board with the AD-QUADMXFE1-EBZ HDL reference design and the ADI Linux kernel for Microblaze. Currently the system uses a Python/IIO interface to the MxFE via the pyadi-iio library, and performs some processing in the Linux user space on the Microblaze processor. As a HW developer I am personally quite new to embedded Linux and IIO, so apologies for any fundamental misunderstandings.
We are aiming to modify the HDL to perform some custom beamforming algorithms. The initial plan is to insert beamforming into the reference design receive chain and pass the single-channel sample stream to the DDR4 memory in the same way that the 32-channel (16 IQ) sample streams are passed in the reference design. Otherwise the HDL will remain largely the same, with a few added configuration registers.
We want to continue to provide the same Python/IIO interfacing to the MxFE with the caveats that the interface now only supplies a single output channel rather than all 16, and the new configuration registers are accessible via the IIO interface. After some initial research, it appears that we would need to modify the linux IIO drivers and underlying HAL drivers as well as device tree information for this to be possible, and it would likely break the current pyadi-iio interface.
With that in mind, what is the recommended path forward for software interface? Would it be easier to write a custom DMA character device for the new sample stream, rather than try to fit it into the existing IIO structure, and then maintain IIO as the configuration interface? Would maintaining the IIO configuration interface even be possible with the new HDL configuration? We for sure want to maintain a Linux operating system (not baremetal), but do not want to add a massive amount of development time by requiring an entirely new software interface to the AD9081 chips.
Thank you!