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The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation...
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ADRV9029 Recommended for New Designs
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ADRV9029 on Analog.com

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ADRV9025 - Not able to test Tx BIST tone

mahima90

on Jan 7, 2026

Category: Hardware

Product Number: ADRV9029

Dear Analog team,

On our custom hardware which has Zynq Ultrascale plus MPSoC and ADRV9025, We are able to achieve JESD Link Status as DATA.
We are currently using 13-NLS profile with ORX disabled.

We are not able to achieve BIST tone at 3MHz. It is coming at LO. LO frequency is set at 900MHz.

Any suggestions ?

How can we check JESD TX data without user-space application?

Regards
Mahima

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hardware ADRV9026 / ADRV9029 ADRV9029 Wideband Transceiver IC ADRV9025A RF Integrated Transceivers Show More

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Ramarao

on Jan 7, 2026 8:44 AM
0
Can you reduce the span and check if the LO and BIST tones are together?

When you say BIST, its generated internally using adi_adrv9025_TxTestToneSet() API from ADRV?
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mahima90
on Jan 9, 2026 12:50 AM in reply to Ramarao
0
Dear Ramarao ,

Thank you for the reply.
From the webpage details, we expected the command to inject a 3 MHz tone.

However, with parameter 200000, I am able to see LO + BIST tone.

Please suggest how can we check JESD TX data without user-space application?

Regards
Mahima
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mahima90
on Jan 12, 2026 5:45 AM in reply to mahima90
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Dear Ramarao ,

Please advise how we can verify the JESD TX data without using a user-space application.
The BIST tone is working, but we are unable to observe any data coming into the Xilinx MPSoC through the JESD lanes.

By default, if valid JESD TX data is present on the lanes, should it be automatically processed through the ADRV9025 digital chain and DACs and then transmitted at the RF output ports? Is my understanding correct?

Regards
Mahima
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Ramarao

on Jan 12, 2026 6:26 AM in reply to mahima90
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mahima90 said:
By default, if valid JESD TX data is present on the lanes, should it be automatically processed through the ADRV9025 digital chain and DACs and then transmitted at the RF output ports? Is my understanding correct?

Yes, if data is present from FPGA, that should get transmitted through ADRV if the link is up. What is framer status and deframer status?
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mahima90
on Jan 13, 2026 6:24 AM in reply to Ramarao
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Link is up. DeFramer status is 0x7 and framer status is 0xA.
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mahima90
on Jan 13, 2026 6:24 AM in reply to Ramarao
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Link is up. DeFramer status is 0x7 and framer status is 0xA.
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ADRV9025 - Not able to test Tx BIST tone

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