Category: Datasheet/Specs
Product Number: ADRV9002
I am working on "ADRV9002 Arria10 SoC" setup to evaluate ADRV9002 Frequency Hopping feature. iio_scope is providing option to read&write ADRV9002 register space through SPI interface but, no register address & bit description details available in UG1828. How to populate Hop Table (UG1828/Table 49) entries? How to configure Hopping Table Indexing mode to Automatic Increment? Though HOP, TX_SETUP, RX_SETUP signals are driven from Arria10 FPGA, not very clear on confirming following operation steps.
- Load module
- Load hopping table via iio
- Enable hop and channel setup signal in FPGA
- Pass data and observe on iio_scope.
Need your support to do and confirm above operation steps.
Thanks,
Siva
