Hi ,
I have a using ADRV9371, i have gebnerated build for zcu102 fpga board from ADI hdl git repo with 2024.2 Vivado version, after generating bit file
1. What is the next step to get ADC / DAC data and configure sampling rate of Transciever?
2. If we will download Petalinx imagae for IIO etc then how to control / process data further in PL side of FPGA ?
3. My build bit file is generated with repect to 2024.2 Vivado version so can i work with petalinux image that is om 2023 by ADI?
Please assist for the same.