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Using UART0 via EMIO on PlutoSDR

Category: Software
Software Version: v0.39

I have a PlutoSDR that I am using for a non-standard application. My use-case requires additional UART opened on the PS CPU of the Xilinx FPGA which will be used to enable external control of the PlutoSDR and code running within it over serial commands. I am using the expansion port of PlutoSDR to route-out signals from the CPU via EMIO. So far, I was not able to boot Linux or have uart0 working. By default, PlutoSDR uses uart1 for Linux terminal and uart0 is disabled and not used. My procedure for enabling UART0 is as follows:

1. Modify `system_bd.tcl` as follows to enable UART0 via EMIO:

# Add these two statements where all ports are defined
create_bd_port -dir O uart0_tx
create_bd_port -dir I uart0_rx

# Add these two statements where configuration is set:
ad_ip_parameter sys_ps7 CONFIG.PCW_UART0_PERIPHERAL_ENABLE 1
ad_ip_parameter sys_ps7 CONFIG.PCW_UART0_UART0_IO EMIO

# Add these two statements where connections are made
ad_connect uart0_rx sys_ps7/UART0_rx
ad_connect uart0_tx sys_ps7/UART0_tx

2. Modify `system_constr.xdc` and `system_top.v` to route newly created `uart0_tx/uart0_rx` lines to K13/M12 pins of expansion header. Previous SPI, I2C and other peripherals were removed.

3. Modified both U-boot and Linux DeviceTrees with the following:

// Adding uart0 to Aliases
aliases: aliases {
	ethernet0 = &gem0;
	serial0 = &uart1;
	serial1 = &uart0;
};

// Enabling uart0
&uart0 {
	status="okay";
};

4. Re-build, flash (unlocked bootloader of course), validate that correct values are set for UART0 registers from U-Boot.

5. Attempt to boot Linux (ramboot, qspiboot, does not matter). And this is where it all falls apart. If I boot with default, settings, I get this log message and then no more response from UART:

e0000000.serial: ttyPS0 at MMIO 0xe0000000 (irq = 27, base_baud = 6249999) is a xuartps
printk: console [ttyPS0] enabled
printk: bootconsole [earlycon0] disabled

This is not what I would expect, since ttyPS0 should be on 0xe0001000, as is specified in devicetree. Probing the UART0 lines, I can see that TX line gets pulled up once FPGA bitstream loads and then spews out repeating garbage after the boot log is displayed. Looking at LED, I can see that boot proceeds forwards, except that I can not interact with the board over any UART.

My initial attempt was to change boot serial port to ttyPS1 via kernel command line, but that fails differently:

e0000000.serial: ttyPS0 at MMIO 0xe0000000 (irq = 27, base_baud = 6249999) is a xuartps
xuartps e0001000.serial: uart_add_one_port() failed; err=-22

Now, board is hung, does not complete its boot up.

I have managed to narrow down, that as soon as I mark `UART0` as enabled in device tree, all problems start to appear. Has any one encountered something similar or have any information in regards to getting uart0 working on PlutoSDR? I am starting to go bald from this issue.

As additional troubleshooting/debugging steps, I tried:

1. Adding SPI pehipheral on PS CPU over EMIO to validate my changes and processes - SPI Works, but this is not what I need.

2. Adding UART over AXI bus - could not get it to work, system boots fine, but hangs as soon as I try to interact with the peripheral. This is probably a different quest tree I have to resolve to get it working.

3. Mucking around with device tree, changing serial port order, messing with boot params - always same result as described above.

4. Rolling back versions of xuartps driver to older ones - always fails, haven't found a working version.

5. Messing around with CONFIG_DEBUG_ZYNQ_UART<0/1> - no change, always the same failure.

  • Hi,

    Can you give us a diff on the devicetrees you modified?

    Andrei

  • Hey Andrei, of course. I will be adding them as attachments so as not to bloat the post too much, if that's OK.

    U-Boot diff:

    diff --git a/arch/arm/dts/zynq-pluto-sdr.dts b/arch/arm/dts/zynq-pluto-sdr.dts
    index c618d98b543..f5492c3a9f5 100644
    --- a/arch/arm/dts/zynq-pluto-sdr.dts
    +++ b/arch/arm/dts/zynq-pluto-sdr.dts
    @@ -15,6 +15,7 @@
     	aliases {
     		ethernet0 = &gem0;
     		serial0 = &uart1;
    +		serial1 = &uart0;
     		spi0 = &qspi;
     	};
     
    @@ -66,6 +67,10 @@
     	};
     };
     
    +&uart0 {
    +	status = "okay";
    +};
    +
     &uart1 {
     	status = "okay";
     };
    diff --git a/configs/zynq_pluto_defconfig b/configs/zynq_pluto_defconfig
    index 0daf46221e5..199c38b72fa 100644
    --- a/configs/zynq_pluto_defconfig
    +++ b/configs/zynq_pluto_defconfig
    @@ -7,7 +7,7 @@ CONFIG_SPL=y
     CONFIG_FIT=y
     CONFIG_FIT_VERBOSE=y
     CONFIG_FIT_SIGNATURE=y
    -CONFIG_BOOTDELAY=0
    +CONFIG_BOOTDELAY=5
     CONFIG_SYS_NO_FLASH=y
     CONFIG_HUSH_PARSER=y
     CONFIG_SYS_PROMPT="Pluto> "
    

    Linux kernel diff:

    diff --git a/arch/arm/boot/dts/zynq-pluto-sdr-revb.dts b/arch/arm/boot/dts/zynq-pluto-sdr-revb.dts
    index 0df55ea39579..f8349e13a2f4 100644
    --- a/arch/arm/boot/dts/zynq-pluto-sdr-revb.dts
    +++ b/arch/arm/boot/dts/zynq-pluto-sdr-revb.dts
    @@ -17,16 +17,6 @@
     #include <dt-bindings/gpio/gpio.h>
     #include <dt-bindings/interrupt-controller/irq.h>
     
    -&axi_i2c0 {
    -	current_limiter@5a {
    -		compatible = "adi,adm1177-iio";
    -		reg = <0x5a>;
    -		adi,r-sense-mohm = <50>; /* 50 mOhm */
    -		adi,shutdown-threshold-ma = <1059>; /* 1.059 A */
    -		adi,vrange-high-enable;
    -	};
    -};
    -
     / {
     	model = "Analog Devices PlutoSDR Rev.B (Z7010/AD9363)";
     
    diff --git a/arch/arm/boot/dts/zynq-pluto-sdr-revc.dts b/arch/arm/boot/dts/zynq-pluto-sdr-revc.dts
    index fe5569225fd3..e33b06f6849c 100644
    --- a/arch/arm/boot/dts/zynq-pluto-sdr-revc.dts
    +++ b/arch/arm/boot/dts/zynq-pluto-sdr-revc.dts
    @@ -60,29 +60,6 @@ iio_axi_tdd_0@0 {
     		"out_channel2_off_raw", "out_channel2_off_ms";
     		label = "iio-axi-tdd-0";
     	};
    -
    -	axi_spi: spi@7C430000 {
    -		#address-cells = <1>;
    -		#size-cells = <0>;
    -		bits-per-word = <8>;
    -		compatible = "xlnx,xps-spi-2.00.a";
    -		fifo-size = <16>;
    -		interrupt-parent = <&intc>;
    -		interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
    -		cs-gpios = <&gpio0 49 0>;
    -		num-cs = <0x1>;
    -		reg = <0x7C430000 0x10000>;
    -		xlnx,num-ss-bits = <0x1>;
    -		xlnx,spi-mode = <0>;
    -
    -		spidev0: spidev@0 {
    -			compatible = "adi,swspi";
    -			reg = <0>;	/* CE0 */
    -			#address-cells = <1>;
    -			#size-cells = <0>;
    -			spi-max-frequency = <125000000>;
    -		};
    -	};
     };
     
     &adc0_ad9364 {
    @@ -119,24 +96,4 @@ button {
     			linux,code = <BTN_MISC>;
     		};
     	};
    -
    -	one-bit-adc-dac@0 {
    -		compatible = "adi,one-bit-adc-dac";
    -
    -		#address-cells = <1>;
    -		#size-cells = <0>;
    -
    -		in-gpios = <&gpio0 71 GPIO_ACTIVE_HIGH>;
    -		out-gpios = <&gpio0 68 GPIO_ACTIVE_HIGH>;
    -
    -		channel@0 {
    -			reg = <0>;
    -			label = "muxout";
    -		};
    -
    -		channel@1 {
    -			reg = <1>;
    -			label = "phaser_enable";
    -		};
    -	};
     };
    diff --git a/arch/arm/boot/dts/zynq-pluto-sdr.dts b/arch/arm/boot/dts/zynq-pluto-sdr.dts
    index eca438ae1fad..09f0cfc299d4 100644
    --- a/arch/arm/boot/dts/zynq-pluto-sdr.dts
    +++ b/arch/arm/boot/dts/zynq-pluto-sdr.dts
    @@ -14,17 +14,6 @@
     /dts-v1/;
     #include "zynq-pluto-sdr.dtsi"
     
    -
    -&axi_i2c0 {
    -	current_limiter@5a {
    -		compatible = "adi,adm1177-iio";
    -		reg = <0x5a>;
    -		adi,r-sense-mohm = <50>; /* 50 mOhm */
    -		adi,shutdown-threshold-ma = <1059>; /* 1.059 A */
    -		adi,vrange-high-enable;
    -	};
    -};
    -
     / {
     	leds {
     		compatible = "gpio-leds";
    diff --git a/arch/arm/boot/dts/zynq-pluto-sdr.dtsi b/arch/arm/boot/dts/zynq-pluto-sdr.dtsi
    index 08c5a42204f3..be7e470fee97 100644
    --- a/arch/arm/boot/dts/zynq-pluto-sdr.dtsi
    +++ b/arch/arm/boot/dts/zynq-pluto-sdr.dtsi
    @@ -97,19 +97,6 @@ fpga_axi: fpga-axi@0 {
     		#size-cells = <0x1>;
     		ranges;
     
    -		axi_i2c0: i2c@41600000 {
    -			compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
    -			reg = <0x41600000 0x10000>;
    -			interrupt-parent = <&intc>;
    -			interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
    -			clocks = <&clkc 15>;
    -			clock-names = "pclk";
    -
    -			#address-cells = <1>;
    -			#size-cells = <0>;
    -
    -		};
    -
     		rx_dma: dma@7c400000 {
     			compatible = "adi,axi-dmac-1.00.a";
     			reg = <0x7c400000 0x1000>;
    diff --git a/arch/arm/boot/dts/zynq.dtsi b/arch/arm/boot/dts/zynq.dtsi
    index 465f00e21edd..38173a7f21e5 100644
    --- a/arch/arm/boot/dts/zynq.dtsi
    +++ b/arch/arm/boot/dts/zynq.dtsi
    @@ -7,6 +7,7 @@ / {
     	aliases: aliases {
     		ethernet0 = &gem0;
     		serial0 = &uart1;
    +		serial1 = &uart0;
     	};
     };
     
    @@ -23,6 +24,10 @@ &usb0 {
     	dr_mode = "host"; /* This breaks OTG mode */
     };
     
    +&uart0 {
    +	status="okay";
    +};
    +
     &uart1 {
     	status = "okay";
     };
    

    For completeness, I am also including the diff of changes I made to HDL:

    diff --git a/projects/pluto/system_bd.tcl b/projects/pluto/system_bd.tcl
    index 0133b3f04..f9053f7dc 100644
    --- a/projects/pluto/system_bd.tcl
    +++ b/projects/pluto/system_bd.tcl
    @@ -26,17 +26,12 @@ create_bd_port -dir I -from 17 -to 0 gpio_i
     create_bd_port -dir O -from 17 -to 0 gpio_o
     create_bd_port -dir O -from 17 -to 0 gpio_t
     
    -create_bd_port -dir O spi_csn_o
    -create_bd_port -dir I spi_csn_i
    -create_bd_port -dir I spi_clk_i
    -create_bd_port -dir O spi_clk_o
    -create_bd_port -dir I spi_sdo_i
    -create_bd_port -dir O spi_sdo_o
    -create_bd_port -dir I spi_sdi_i
    -
     create_bd_port -dir O txdata_o
     create_bd_port -dir I tdd_ext_sync
     
    +create_bd_port -dir O uart0_tx
    +create_bd_port -dir I uart0_rx
    +
     # instance: sys_ps7
     
     ad_ip_instance processing_system7 sys_ps7
    @@ -56,6 +51,8 @@ ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1
     ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 18
     ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 0
     ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 0
    +ad_ip_parameter sys_ps7 CONFIG.PCW_UART0_PERIPHERAL_ENABLE 1
    +ad_ip_parameter sys_ps7 CONFIG.PCW_UART0_UART0_IO EMIO
     ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE 1
     ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}
     ad_ip_parameter sys_ps7 CONFIG.PCW_I2C1_PERIPHERAL_ENABLE 0
    @@ -102,13 +99,6 @@ ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
     
     # system reset/clock definitions
     
    -# add external spi
    -
    -ad_ip_instance axi_quad_spi axi_spi
    -ad_ip_parameter axi_spi CONFIG.C_USE_STARTUP 0
    -ad_ip_parameter axi_spi CONFIG.C_NUM_SS_BITS 1
    -ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 8
    -
     ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
     ad_connect  sys_200m_clk sys_ps7/FCLK_CLK1
     ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
    @@ -136,16 +126,10 @@ ad_connect  spi0_sdo_i sys_ps7/SPI0_MOSI_I
     ad_connect  spi0_sdo_o sys_ps7/SPI0_MOSI_O
     ad_connect  spi0_sdi_i sys_ps7/SPI0_MISO_I
     
    -# axi spi connections
    +# ps7 uart connections
     
    -ad_connect  sys_cpu_clk  axi_spi/ext_spi_clk
    -ad_connect  spi_csn_i  axi_spi/ss_i
    -ad_connect  spi_csn_o  axi_spi/ss_o
    -ad_connect  spi_clk_i  axi_spi/sck_i
    -ad_connect  spi_clk_o  axi_spi/sck_o
    -ad_connect  spi_sdo_i  axi_spi/io0_i
    -ad_connect  spi_sdo_o  axi_spi/io0_o
    -ad_connect  spi_sdi_i  axi_spi/io1_i
    +ad_connect uart0_rx sys_ps7/UART0_rx
    +ad_connect uart0_tx sys_ps7/UART0_tx
     
     # interrupts
     
    @@ -167,16 +151,6 @@ ad_connect  sys_concat_intc/In2 GND
     ad_connect  sys_concat_intc/In1 GND
     ad_connect  sys_concat_intc/In0 GND
     
    -# iic
    -
    -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
    -
    -ad_ip_instance axi_iic axi_iic_main
    -
    -ad_connect  iic_main axi_iic_main/iic
    -ad_cpu_interconnect 0x41600000 axi_iic_main
    -ad_cpu_interrupt ps-15 mb-15 axi_iic_main/iic2intc_irpt
    -
     # ad9361
     
     create_bd_port -dir I rx_clk_in
    @@ -349,7 +323,6 @@ ad_connect axi_tdd_0/tdd_channel_2 axi_ad9361_dac_dma/sync
     ad_cpu_interconnect 0x79020000 axi_ad9361
     ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
     ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
    -ad_cpu_interconnect 0x7C430000 axi_spi
     ad_cpu_interconnect 0x7C440000 axi_tdd_0
     
     ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 {1}
    @@ -379,5 +352,4 @@ ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
     
     ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
     ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
    -ad_cpu_interrupt ps-11 mb-11 axi_spi/ip2intc_irpt
     
    diff --git a/projects/pluto/system_constr.xdc b/projects/pluto/system_constr.xdc
    index 59611ccc8..5856941f6 100644
    --- a/projects/pluto/system_constr.xdc
    +++ b/projects/pluto/system_constr.xdc
    @@ -61,21 +61,8 @@ set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVCMOS18} [get_ports spi_clk]
     set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVCMOS18} [get_ports spi_mosi]
     set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports spi_miso]
     
    -# PL GPIOs
    -#
    -# Pin  | Package Pin | GPIO     | Pluto    | Phaser  |
    -# -----|-------------|----------|----------|---------|
    -# L10P | K13         | PL_GPIO0 | SPI MOSI | TXDATA  |
    -# L12N | M12         | PL_GPIO1 | SPI MISO | BURST   |
    -# L24N | R10         | PL_GPIO2 | SPI CLKO | MUXOUT  |
    -# L7N  | N14         | PL_GPIO3 | IIC SDA  | IIC SDA |
    -# L9N  | M14         | PL_GPIO4 | IIC SCL  | IIC SCL |
    -
    -set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVCMOS18} [get_ports pl_gpio0]
    -set_property  -dict {PACKAGE_PIN  M12  IOSTANDARD LVCMOS18} [get_ports pl_gpio1]
    -set_property  -dict {PACKAGE_PIN  R10  IOSTANDARD LVCMOS18} [get_ports pl_gpio2]
    -set_property  -dict {PACKAGE_PIN  N14  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports pl_gpio3]
    -set_property  -dict {PACKAGE_PIN  M14  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports pl_gpio4]
    +set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports periph_uart_tx]
    +set_property  -dict {PACKAGE_PIN  M12  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports periph_uart_rx]
     
     set_property  -dict {PACKAGE_PIN  P8   IOSTANDARD LVCMOS18} [get_ports clk_out]
     
    diff --git a/projects/pluto/system_top.v b/projects/pluto/system_top.v
    index acb97bb70..d72dc65de 100644
    --- a/projects/pluto/system_top.v
    +++ b/projects/pluto/system_top.v
    @@ -81,11 +81,8 @@ module system_top (
       output          spi_mosi,
       input           spi_miso,
     
    -  output          pl_gpio0,
    -  input           pl_gpio1,
    -  inout           pl_gpio2,
    -  inout           pl_gpio3,
    -  inout           pl_gpio4
    +  output          periph_uart_tx,
    +  input           periph_uart_rx
     );
     
       // internal signals
    @@ -94,14 +91,7 @@ module system_top (
       wire    [17:0]  gpio_o;
       wire    [17:0]  gpio_t;
     
    -  wire            iic_scl;
    -  wire            iic_sda;
    -  wire            phaser_enable;
       wire            pl_burst;
    -  wire            pl_muxout;
    -  wire            pl_spi_clk_o;
    -  wire            pl_spi_miso;
    -  wire            pl_spi_mosi;
       wire            pl_txdata;
     
       // instantiations
    @@ -118,27 +108,6 @@ module system_top (
                   gpio_status}));     //  7: 0
     
       assign gpio_i[16:14] = gpio_o[16:14];
    -  assign gpio_i[17] = pl_muxout;
    -  assign phaser_enable = gpio_o[14];
    -
    -  assign pl_gpio4 = iic_scl;      //PL_GPIO4
    -  assign pl_gpio3 = iic_sda;      //PL_GPIO3
    -
    -  //PL_GPIO2
    -  ad_iobuf #(
    -    .DATA_WIDTH(1)
    -  ) i_pl_gpio_iobuf (
    -    .dio_t (phaser_enable),
    -    .dio_i (pl_spi_clk_o),
    -    .dio_o (pl_muxout),
    -    .dio_p (pl_gpio2));
    -
    -  //PL_GPIO1
    -  assign pl_spi_miso = pl_gpio1 & ~phaser_enable;
    -  assign pl_burst    = pl_gpio1 &  phaser_enable;
    -
    -  //PL_GPIO0
    -  assign pl_gpio0 = phaser_enable ? pl_txdata : pl_spi_mosi;
     
       system_wrapper i_system_wrapper (
         .ddr_addr (ddr_addr),
    @@ -166,8 +135,6 @@ module system_top (
         .gpio_i (gpio_i),
         .gpio_o (gpio_o),
         .gpio_t (gpio_t),
    -    .iic_main_scl_io (iic_scl),
    -    .iic_main_sda_io (iic_sda),
         .rx_clk_in (rx_clk_in),
         .rx_data_in (rx_data_in),
         .rx_frame_in (rx_frame_in),
    @@ -182,13 +149,8 @@ module system_top (
         .spi0_sdo_i (1'b0),
         .spi0_sdo_o (spi_mosi),
     
    -    .spi_clk_i(1'b0),
    -    .spi_clk_o(pl_spi_clk_o),
    -    .spi_csn_i(1'b1),
    -    .spi_csn_o(),
    -    .spi_sdi_i(pl_spi_miso),
    -    .spi_sdo_i(1'b0),
    -    .spi_sdo_o(pl_spi_mosi),
    +    .uart0_tx (periph_uart_tx),
    +    .uart0_rx (periph_uart_rx),
     
         .tdd_ext_sync(pl_burst),
         .txdata_o(pl_txdata),
    diff --git a/projects/scripts/project-xilinx.mk b/projects/scripts/project-xilinx.mk
    index c7431de2d..a61cb5eab 100644
    --- a/projects/scripts/project-xilinx.mk
    +++ b/projects/scripts/project-xilinx.mk
    @@ -19,7 +19,7 @@ ifdef CFG
         DIR_NAME := $(basename $(notdir $(CFG)))
     endif
     
    -VIVADO := vivado -mode batch -source
    +VIVADO := LD_PRELOAD=/lib/x86_64-linux-gnu/libudev.so.1 vivado -mode batch -source
     
     # Parse the variables passed to make and convert them to the filename format
     CMD_VARIABLES := $(shell echo $(-*-command-variables-*-) | tac -s ' ')
    diff --git a/scripts/adi_env.tcl b/scripts/adi_env.tcl
    index 53eae54d1..4c999a073 100644
    --- a/scripts/adi_env.tcl
    +++ b/scripts/adi_env.tcl
    @@ -15,7 +15,7 @@ if [info exists ::env(ADI_GHDL_DIR)] {
     }
     
     # Define the supported tool version
    -set required_vivado_version "2023.2"
    +set required_vivado_version "2023.2.2"
     if {[info exists ::env(REQUIRED_VIVADO_VERSION)]} {
       set required_vivado_version $::env(REQUIRED_VIVADO_VERSION)
     } elseif {[info exists REQUIRED_VIVADO_VERSION]} {
    

    There were no changes made to Buildroot or base PlutoSDR project.

  • Hi,

    My perspective comes as an HDL person.
    I don't see anything wrong in HDL. 
    To me the device tree looks ok.

    I suspect there is something wrong after u-boot (second stage bootloader). Because you get messages from the first stage bootloader.
    Waiting for someone from the Linux team to doublecheck.

    Andrei

  • Thank you for confirming HDL changes are correct, this eliminates problem space greatly. My hunch is also that this is Linux/driver issue, will be waiting for some input from Linux people.