I plan to modify the sampling rates of both the DAC and ADC to 500 MSPS from the default 250 MSPS . Based on my analysis, this requires updating the JESD configuration within the HDL. I have revised the HDL parameters as follows: JESD_MODE = 8 B10B RX_LANE_RATE = 10 TX_LANE_RATE = 10 RX_JESD_M = 8 RX_JESD_L = 8 RX_JESD_S = 1 TX_JESD_M = 8 TX_JESD_L = 8 TX_JESD_S = 1 In the device tree source file: https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4.dts , Is modifying RX_JESD_L = 8 , TX_JESD_L = 8 , interpolation , and decimation sufficient, or are there additional parameters that also need updating? In the AD9081/AD9082 User Guide: https://www.analog.com/media/en/technical-documentation/user-guides/ad9081-ad9082-ug-1578.pdf , several JESD parameters are referenced, including K, F, E, S, and M . I am unclear about their specific roles and usage. Could you please provide clarification? In the zynqmp-zcu102-rev10-ad9081-m8-l4.dts file, what is the relationship between pll2-output-frequency and the divider settings in the HMC7044 channels ? Thank you.

sampling rate

Dhi

on Nov 12, 2025

Category: Hardware

Product Number: AD9081 with ZCU102, AD9081

I plan to modify the sampling rates of both the DAC and ADC to 500 MSPS from the default 250 MSPS. Based on my analysis, this requires updating the JESD configuration within the HDL. I have revised the HDL parameters as follows:

In the device tree source file:
https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4.dts,
Is modifying RX_JESD_L = 8, TX_JESD_L = 8, interpolation, and decimation sufficient, or are there additional parameters that also need updating?
In the AD9081/AD9082 User Guide:
https://www.analog.com/media/en/technical-documentation/user-guides/ad9081-ad9082-ug-1578.pdf,
several JESD parameters are referenced, including K, F, E, S, and M. I am unclear about their specific roles and usage. Could you please provide clarification?
In the zynqmp-zcu102-rev10-ad9081-m8-l4.dts file, what is the relationship between pll2-output-frequency and the divider settings in the HMC7044 channels?

Thank you.

Thread Notes

Clock Generation Devices Clock Generation and Distribution hardware AD9081 High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE) AD9081 with ZCU102 Show More

danmois

on Nov 12, 2025 5:35 AM
0
Hi Dhi ,

1. The AD9081/AD9082 User Guide contains various use cases. One can be picked for there, implemented in the devicetree, and then in the HDL.

2. A good starting point for getting familiar with the ADI JESD FSM is https://analogdevicesinc.github.io/hdl/library/jesd204/index.html

3. The channel's output is pll2-output-frequency / divider.

Regards,

G
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yhkim

on Nov 12, 2025 7:59 AM in reply to danmois
0
Hi, the procedure and files required to change the sample rate from 250MSPS to 500MSPS can be found here: https://ez.analog.com/rf/wide-band-rf-transceivers/mixed-signal-front-ends-mxfe/f/q-a/591462/ad9081-zc706-set-lane-rate-failed-when-changing-device-clock-frequency - please find the post dated "Feb 4, 2025". Hope that helps.

-YH
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Dhi
on Nov 12, 2025 8:23 AM in reply to danmois
0
Hi danmois,

danmois said:
The AD9081/AD9082 User Guide contains various use cases. One can be picked for there, implemented in the devicetree, and then in the HDL.

From that user guide, I have picked example 15, and I have created the HDL file accordingly. But while building Petalinux, I need to configure this dts file. In that DTS file, what modifications need to be made?

Dhi said:
RX_JESD_L = 8, TX_JESD_L = 8, interpolation, and decimation

As I mentioned, here only these changes are enough for achieving 500MSPS, or I need to modify (pll2-output-frequency / divider) combination also to 500.

In my HDL design, I saw RX_JESD_F=4, TX_JESD_L=4. As I saw in the User Guide, to set the Interpolation values, I was not able to find this combination (L=8, M=8, F=4, S=1, N=16, K=32), only I have seen (L=8, M=8, F=2, S=1, N=16, K=32) combination. Is there any reason for that? Is there any connection between the "adi,link-mode = <9>; /* JESD Quick Configuration Mode */ " line in DTS and JESD parameters?

Thank you.
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Dhi
on Nov 13, 2025 1:25 AM in reply to yhkim
0
Hi yhkim,

This Forum is really useful. Still, I am having a few clarifications that early I have mention.

Thanks.
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Dhi

on Nov 13, 2025 4:51 AM in reply to yhkim

Hi yhkim,

yhkim said:
: https://ez.analog.com/rf/wide-band-rf-transceivers/mixed-signal-front-ends-mxfe/f/q-a/591462/ad9081-zc706-set-lane-rate-failed-when-changing-device-clock-frequency

After configuring the changes provided in the .dts file at that link, I am getting this. I have configured everything as it is in my .dts file.

6428.Boot_log.txt

Even after configuring everything, I am receiving this

[ 10.911855] cf_axi_adc 84a10000.axi-ad9081-rx-hpc: profile0:link_num2 param L mismatch 8!=4*1
[ 10.920375] cf_axi_adc 84a10000.axi-ad9081-rx-hpc: profile0:link_num2 param F mismatch 2!=4
[ 10.928724] cf_axi_adc 84a10000.axi-ad9081-rx-hpc: JESD param mismatch between TPL and Link configuration!
[ 10.938457] cf_axi_dds 84b10000.axi-ad9081-tx-hpc: profile0:link_num0 param L mismatch 8!=4*1
[ 10.946978] cf_axi_dds 84b10000.axi-ad9081-tx-hpc: profile0:link_num0 param F mismatch 2!=4

My .dts file is not configuring properly for my project. Can you help me understand why my .dts file and project are not syncing properly? What may be the process

I have created as mentioned here" https://github.com/analogdevicesinc/meta-adi/tree/main/meta-adi-xilinx ".

Thank you.

yhkim

on Nov 14, 2025 3:21 AM in reply to Dhi
0
It appears that there are mismatches between HDL and Linux driver. Could you confirm you have updated HDL with L=8? Could you share your HDL parameters and dts file, we may be able to try them sometime early next week.

-YH

One question: Have you tried with Kuiper Linux before trying Petalinux?

You may want to review this thread: https://ez.analog.com/linux-software-drivers/f/q-a/600390/running-the-adi-hdl-reference-design-with-petalinux---how-to-select-the-device-tree,
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Dhi

on Nov 14, 2025 5:25 AM in reply to yhkim

yhkim said:
Could you confirm you have updated HDL with L=8?

I have updated HDL with L=8.

yhkim said:
dts file

// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices AD9081-FMC-EBZ
* wiki.analog.com/.../quick-start
* wiki.analog.com/.../ad9081
*
* hdl_project: <ad9081_fmca_ebz/zcu102>
* board_revision: <>
*
* Copyright (C) 2019-2020 Analog Devices Inc.
*/

#include "zynqmp-zcu102-rev10-ad9081-default.dtsi"
#include <dt-bindings/iio/frequency/hmc7044.h>
#include <dt-bindings/iio/adc/adi,ad9081.h>

&axi_ad9081_adxcvr_rx {
adi,sys-clk-select = <XCVR_CPLL>;
};

&spi1 {
status = "okay";

hmc7044: hmc7044@0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
compatible = "adi,hmc7044";
reg = <0>;
spi-max-frequency = <1000000>;

jesd204-device;
#jesd204-cells = <2>;
jesd204-sysref-provider;

adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */

/*
* There are different versions of the AD9081-FMCA-EBZ & AD9082-FMCA-EBZ
* VCXO = 122.880 MHz, XO = 122.880MHz (AD9081-FMC-EBZ & AD9082-FMC-EBZ)
* VCXO = 100.000 MHz, XO = 100.000MHz (AD9081-FMC-EBZ-A2 & AD9082-FMC-EBZ-A2)
* To determine which board is which, read the freqency printed on the VCXO
* or use the fru-dump utility:
* #fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
*/

//adi,pll1-clkin-frequencies = <122880000 30720000 0 0>;
//adi,vcxo-frequency = <122880000>;

adi,pll1-clkin-frequencies = <100000000 10000000 0 0>;
adi,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */
adi,pll1-ref-autorevert-enable;
adi,vcxo-frequency = <100000000>;

adi,pll1-loop-bandwidth-hz = <200>;
adi,pll1-charge-pump-current-ua = <720>;
adi,pfd1-maximum-limit-frequency-hz = <1000000>; /* 1 MHz */

adi,pll2-output-frequency = <3000000000>;

adi,sysref-timer-divider = <1024>;
adi,pulse-generator-mode = <0>;

adi,clkin0-buffer-mode = <0x07>;
adi,clkin1-buffer-mode = <0x07>;
adi,oscin-buffer-mode = <0x15>;

adi,gpi-controls = <0x00 0x00 0x00 0x00>;
adi,gpo-controls = <0x37 0x33 0x00 0x00>;

clock-output-names =
"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
"hmc7044_out12", "hmc7044_out13";

hmc7044_c0: channel@0 {
reg = <0>;
adi,extended-name = "CORE_CLK_RX";
adi,divider = <12>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;

};
hmc7044_c2: channel@2 {
reg = <2>;
adi,extended-name = "DEV_REFCLK";
adi,divider = <12>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c3: channel@3 {
reg = <3>;
adi,extended-name = "DEV_SYSREF";
adi,divider = <1536>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
adi,jesd204-sysref-chan;
};

hmc7044_c6: channel@6 {
reg = <6>;
adi,extended-name = "CORE_CLK_TX";
adi,divider = <12>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};

hmc7044_c8: channel@8 {
reg = <8>;
adi,extended-name = "FPGA_REFCLK1";
adi,divider = <6>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c10: channel@10 {
reg = <10>;
adi,extended-name = "CORE_CLK_RX_ALT";
adi,divider = <12>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};

hmc7044_c12: channel@12 {
reg = <12>;
adi,extended-name = "FPGA_REFCLK2";
adi,divider = <6>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c13: channel@13 {
reg = <13>;
adi,extended-name = "FPGA_SYSREF";
adi,divider = <1536>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
adi,jesd204-sysref-chan;
};
};
};

&fmc_spi {

trx0_ad9081: ad9081@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,ad9081";
reg = <0>;
spi-max-frequency = <5000000>;

/* Clocks */
clocks = <&hmc7044 2>;
clock-names = "dev_clk";

clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <1>;

jesd204-device;
#jesd204-cells = <2>;
jesd204-top-device = <0>; /* This is the TOP device */
jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;

jesd204-inputs =
<&axi_ad9081_core_rx 0 FRAMER_LINK0_RX>,
<&axi_ad9081_core_tx 0 DEFRAMER_LINK0_TX>;

adi,tx-dacs {
#size-cells = <0>;
#address-cells = <1>;

adi,dac-frequency-hz = /bits/ 64 <12000000000>;

adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;

adi,interpolation = <8>;

ad9081_dac0: dac@0 {
reg = <0>;
adi,crossbar-select = <&ad9081_tx_fddc_chan0>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 100 MHz */
};
ad9081_dac1: dac@1 {
reg = <1>;
adi,crossbar-select = <&ad9081_tx_fddc_chan1>;
adi,nco-frequency-shift-hz = /bits/ 64 <1100000000>; /* 200 MHz */
};
ad9081_dac2: dac@2 {
reg = <2>;
adi,crossbar-select = <&ad9081_tx_fddc_chan2>; /* All 4 channels @ dac2 */
adi,nco-frequency-shift-hz = /bits/ 64 <1200000000>; /* 300 MHz */
};
ad9081_dac3: dac@3 {
reg = <3>;
adi,crossbar-select = <&ad9081_tx_fddc_chan3>; /* All 4 channels @ dac2 */
adi,nco-frequency-shift-hz = /bits/ 64 <1300000000>; /* 400 MHz */
};
};

adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <3>;

ad9081_tx_fddc_chan0: channel@0 {
reg = <0>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;

};
ad9081_tx_fddc_chan1: channel@1 {
reg = <1>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;

};
ad9081_tx_fddc_chan2: channel@2 {
reg = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;

};
ad9081_tx_fddc_chan3: channel@3 {
reg = <3>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;

};
};

adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;

ad9081_tx_jesd_l0: link@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;

adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;

adi,link-mode = <15>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <1>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */

adi,converters-per-device = <8>; /* JESD M */
adi,octets-per-frame = <2>; /* JESD F */

adi,frames-per-multiframe = <32>; /* JESD K */
adi,converter-resolution = <16>; /* JESD N */
adi,bits-per-sample = <16>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <8>; /* JESD L */
adi,samples-per-converter-per-frame = <1>; /* JESD S */
adi,high-density = <0>; /* JESD HD */
adi,tpl-phase-adjust = <3>;
};
};
};

adi,rx-adcs {
#size-cells = <0>;
#address-cells = <1>;

adi,adc-frequency-hz = /bits/ 64 <4000000000>;

adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;

ad9081_adc0: adc@0 {
reg = <0>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <400000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
//adi,crossbar-select = <&ad9081_rx_fddc_chan0>, <&ad9081_rx_fddc_chan2>; /* Static for now */
};
ad9081_adc1: adc@1 {
reg = <1>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <(-400000000)>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
//adi,crossbar-select = <&ad9081_rx_fddc_chan1>, <&ad9081_rx_fddc_chan3>; /* Static for now */
};
ad9081_adc2: adc@2 {
reg = <2>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <100000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
//adi,crossbar-select = <&ad9081_rx_fddc_chan4>, <&ad9081_rx_fddc_chan6>; /* Static for now */
};
ad9081_adc3: adc@3 {
reg = <3>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <100000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
//adi,crossbar-select = <&ad9081_rx_fddc_chan5>, <&ad9081_rx_fddc_chan7>; /* Static for now */
};
};

adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;

ad9081_rx_fddc_chan0: channel@0 {
reg = <0>;
adi,decimation = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;

};
ad9081_rx_fddc_chan1: channel@1 {
reg = <1>;
adi,decimation = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;

};
ad9081_rx_fddc_chan4: channel@4 {
reg = <4>;
adi,decimation = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;

};
ad9081_rx_fddc_chan5: channel@5 {
reg = <5>;
adi,decimation = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;

};
};

adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;

ad9081_rx_jesd_l0: link@0 {
reg = <0>;
adi,converter-select =
<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>,
<&ad9081_rx_fddc_chan4 FDDC_I>, <&ad9081_rx_fddc_chan4 FDDC_Q>,
<&ad9081_rx_fddc_chan5 FDDC_I>, <&ad9081_rx_fddc_chan5 FDDC_Q>;

adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;

adi,link-mode = <16>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <1>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */

adi,converters-per-device = <8>; /* JESD M */
adi,octets-per-frame = <2>; /* JESD F */

yhkim said:
your HDL parameters

JESD_MODE = 8B10B RX_LANE_RATE = 10 TX_LANE_RATE = 10 RX_JESD_M = 8 RX_JESD_L = 8 RX_JESD_S = 1 TX_JESD_M = 8 TX_JESD_L = 8 TX_JESD_S = 1

So far, I've learned that this .dts file is not configured with my project. Only the default .dts file( 250MSPS) is configured with my Petalinux project. I was not aware of how to configure a custom .dts with a project.

yhkim said:
Have you tried with Kuiper Linux before trying Petalinux?

No, I never used Kuiper Linux and don't know how to use it.

Kindly help me to configure the custom .dts for my PetaLinux project.

-Dhi.

mhennerich

on Nov 20, 2025 11:40 AM in reply to Dhi
0
If you want to go form 250MSPS to 500MSPS, and you go from L=4 to L=8 the lane rate remains constant.

Therefore the clocks won't change. You need to adjust the overall decimation and interpolation accordingly.

You also need to adjust the JESD Parameters accordingly including the adi,link-mode.

To do so you need to visit the supported DAC/ADC path settings in the User Guide, be aware certain modes only support certain interpolation and decimation distributions.

If you rebuild the HDL with the proper synthesis parameters and use this build with the updated devicetree, things should work.

-Michael
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mhennerich

on Nov 20, 2025 11:42 AM in reply to mhennerich
0
BTW - there is pyadi-jif which can assist you with the mode selection.

Please see here: JIF Tools Explorer — pyadi-jif v0.1.4 documentation

-Michael
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Dhi
on Dec 12, 2025 4:52 AM in reply to mhennerich
0
Hi mhennerich,

mhennerich said:
If you want to go form 250MSPS to 500MSPS, and you go from L=4 to L=8 the lane rate remains constant.

That combination is configured in "system_user.dtsi", and after that, the sampling rate was changed to 500 MSPS. After changing the sampling rate to 500 MSPS and testing the example IQ files, I started seeing issues. When I enable DAC Buffer Output and transmit the example file Sinewave_0.3.mat, only the I (real) component is transmitted, while the Q component is always zero, and I observe two peaks in the output.

I also noticed that the DDS single-tone frequency is being transmitted along with these .txt files. At 250 MSPS, everything works without any problem.

What might be causing this, and how can I fix it? Any suggestions would be helpful.
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