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Using libiio over PCIe between ZU4EG FPGA (Endpoint) and Jetson Host with AD9361

Thread Summary

The user inquires about streaming AD9361 ADC samples from a Zynq UltraScale+ ZU4EG FPGA to an NVIDIA Jetson platform via PCIe using libiio. The final answer confirms that libiio does not support PCIe transport directly, and data must be routed through the ARM on the Zynq. ADI does not provide PCIe IP or reference implementations for data movement. The fastest supported interfaces by libiio are Ethernet or USB.
AI Generated Content
Category: Software
Product Number: ad9361
Software Version: Petalinux-v2023.2

Hi Team,

We are currently evaluating the possibility of streaming AD9361 ADC samples from an FPGA (Zynq UltraScale+ ZU4EG) to an NVIDIA Jetson platform through PCIe using the libiio framework.

Setup details:

  • Transceiver: AD9361

  • FPGA: ZU4EG (configured as PCIe Endpoint)

  • Host: Jetson (Linux-based, acts as PCIe Root Complex)

  • Goal: Transfer ADC samples acquired through the AD9361 interface in FPGA fabric to Jetson via PCIe and access them using libiio (IIO context).

We want to confirm:

  1. Whether libiio supports PCIe transport between a Xilinx FPGA (Endpoint) and a Jetson host.

  2. If yes, what driver or setup is recommended for the FPGA endpoint side and Jetson host side?

  3. If not supported, what alternative interface ADI recommends for high-speed sample streaming from FPGA to Jetson using IIO.

Thank you very much for your guidance and support.

  • No. The fastest interface libiio supports is either Ethernet or USB.

    Architecturally today libiio routes data through the ARM on Zynqs. If you wanted to use libiio you would need to implement a backend to route PCIe traffic to the ARM.

    -Travis

  • Thank you for the clarification.

    Just to confirm my understanding — using libiio directly over PCIe between the ZU4EG FPGA (configured as a PCIe endpoint) and the Jetson host is not currently supported in the standard libiio framework, correct? In that case, implementing a custom PCIe backend would be required to bridge DMA data and libiio on the Jetson side.

    We are using the AD9361 transceiver, and our goal is to stream ADC samples from the FPGA to the Jetson host via PCIe. Could you please confirm if this approach aligns with how other PCIe-based systems (like ADRV9009-ZU11EG) handle data movement internally, or if those still rely on the embedded ARM?

    Thanks again for your time and guidance.

  • Just to confirm my understanding — using libiio directly over PCIe between the ZU4EG FPGA (configured as a PCIe endpoint) and the Jetson host is not currently supported in the standard libiio framework, correct? In that case, implementing a custom PCIe backend would be required to bridge DMA data and libiio on the Jetson side.

    There is no implementation for PCIe with libiio to my knowledge. You would need to create a data transfer mechanism from the Jetson through the PL to the ARM to talk to IIOD. ADI does not provide any IP here.

    We are using the AD9361 transceiver, and our goal is to stream ADC samples from the FPGA to the Jetson host via PCIe. Could you please confirm if this approach aligns with how other PCIe-based systems (like ADRV9009-ZU11EG) handle data movement internally, or if those still rely on the embedded ARM?

    ADI does not provide PCIe IP. We verify the interfaces electrically but do not provide reference data movement implementations on any platform with PCIe.

    -Travis

  • Hi Travis,

    Thank you for the clarification and quick response.