Dear all,
For current ZCU102 + ADRV9029 eval board, we intend to use the 13-Nonlink sharing profile with an RX sampling rate of 122.88 MHz.
Key configuration details are as follows:
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ORX data lanes will be disabled.
-
Framer 1 will be disabled.
-
The
init.cfiles need to be generated accordingly and placed in thelinux/firmwaredirectory.-
Base version:
2023_R2
-
Additionally, HDL modifications are required to support this configuration:
-
An
axi_clkgenIP core needs to be integrated to allow setting the receive-side clock rate. -
Currently, the
core_clkis being routed to all TPL datapath blocks (e.g.,rx_cpack,rx_dma, etc.).-
This needs to be adjusted so that the RX datapath can be clocked independently using the output from
axi_clkgen.
-
Let us know if there are any additional changes or considerations required on either the HDL or software side to fully support this configuration.
Regards
Mahima


