AD9081
Recommended for New Designs
The AD9081 mixed signal front end (MxFE®) is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter...
Datasheet
AD9081 on Analog.com
HMC7044
Recommended for New Designs
The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise...
HMC7044 on Analog.com
We are trying to use the AD9081 as an 8 channel high speed DAC/ADC system. I see the hardware works fine with the example BOOT.BIN and dtb files. (ie. zynqmp-zcu102-rev10-ad9081-204c-txmode0-rxmode1).
I have verified my build environment is fine and was able to re-create the same working setup from the linux and hdl sources. I am using 2023.R2 for both the Xilinx tools as well as the 2023_R2 tags of the source repositories.
I started with the txmode0_rxmode1 dts as a starting point and modified the 204c and clock settings to what I thought was correct for txmode 35 and rxmode 25.10 with 17.96 GHz as the lane rates for both rx and tx.
The dts is inserted below
#include <dt-bindings/iio/frequency/hmc7044.h>
#include <dt-bindings/iio/adc/adi,ad9081.h>
#include "zynqmp-zcu102-rev10-ad9081-default.dtsi"
&axi_ad9081_rx_jesd {
clocks = <&zynqmp_clk 71>, <&hmc7044 10>, <&axi_ad9081_adxcvr_rx 1>, <&axi_ad9081_adxcvr_rx 0>;
clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";
};
&axi_ad9081_tx_jesd {
clocks = <&zynqmp_clk 71>, <&hmc7044 6>, <&axi_ad9081_adxcvr_tx 1>, <&axi_ad9081_adxcvr_tx 0>;
clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";
};
&axi_ad9081_adxcvr_rx {
adi,sys-clk-select = <XCVR_QPLL>;
adi,out-clk-select = <XCVR_PROGDIV_CLK>;
};
&axi_ad9081_adxcvr_tx {
adi,out-clk-select = <XCVR_REFCLK>;
adi,out-clk-select = <XCVR_PROGDIV_CLK>;
};
&spi1 {
status = "okay";
hmc7044: hmc7044@0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
compatible = "adi,hmc7044";
reg = <0>;
spi-max-frequency = <1000000>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-sysref-provider;
adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */
/*
* There are different versions of the AD9081-FMCA-EBZ & AD9082-FMCA-EBZ
* VCXO = 122.880 MHz, XO = 122.880MHz (AD9081-FMC-EBZ & AD9082-FMC-EBZ)
* VCXO = 100.000 MHz, XO = 100.000MHz (AD9081-FMC-EBZ-A2 & AD9082-FMC-EBZ-A2)
* To determine which board is which, read the freqency printed on the VCXO
* or use the fru-dump utility:
* #fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
*/
//adi,pll1-clkin-frequencies = <122880000 30720000 0 0>;
//adi,vcxo-frequency = <122880000>;
adi,pll1-clkin-frequencies = <100000000 10000000 0 0>;
adi,vcxo-frequency = <100000000>;
adi,pll1-loop-bandwidth-hz = <200>;
adi,pll1-charge-pump-current-ua = <720>;
adi,pfd1-maximum-limit-frequency-hz = <1000000>; /* 1 MHz */
adi,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */
adi,pll1-ref-autorevert-enable;
adi,pll2-output-frequency = <2900000000>;
adi,sysref-timer-divider = <1024>;
adi,pulse-generator-mode = <0>;
adi,clkin0-buffer-mode = <0x07>;
adi,clkin1-buffer-mode = <0x07>;
adi,oscin-buffer-mode = <0x15>;
adi,gpi-controls = <0x00 0x00 0x00 0x00>;
adi,gpo-controls = <0x37 0x33 0x00 0x00>;
clock-output-names =
"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
"hmc7044_out12", "hmc7044_out13";
hmc7044_c0: channel@0 {
reg = <0>;
adi,extended-name = "CORE_CLK_RX";
adi,divider = <24>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
adi.disable;
};
hmc7044_c2: channel@2 {
reg = <2>;
adi,extended-name = "DEV_REFCLK";
adi,divider = <8>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c3: channel@3 {
reg = <3>;
adi,extended-name = "DEV_SYSREF";
adi,divider = <768>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
adi,jesd204-sysref-chan;
};
hmc7044_c6: channel@6 {
reg = <6>;
adi,extended-name = "CORE_CLK_TX";
adi,divider = <24>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c8: channel@8 {
reg = <8>;
adi,extended-name = "FPGA_REFCLK1";
adi,divider = <16>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
adi.disable;
};
hmc7044_c10: channel@10 {
reg = <10>;
adi,extended-name = "CORE_CLK_RX_ALT";
adi,divider = <24>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c12: channel@12 {
reg = <12>;
adi,extended-name = "FPGA_REFCLK2";
adi,divider = <16>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c13: channel@13 {
reg = <13>;
adi,extended-name = "FPGA_SYSREF";
adi,divider = <768>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
adi,jesd204-sysref-chan;
};
};
};
&fmc_spi {
trx0_ad9081: ad9081@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,ad9081";
reg = <0>;
spi-max-frequency = <5000000>;
/* Clocks */
clocks = <&hmc7044 2>;
clock-names = "dev_clk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <1>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-top-device = <0>; /* This is the TOP device */
jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;
jesd204-inputs =
<&axi_ad9081_core_rx 0 FRAMER_LINK0_RX>,
<&axi_ad9081_core_tx 0 DEFRAMER_LINK0_TX>;
adi,tx-dacs {
#size-cells = <0>;
#address-cells = <1>;
adi,dac-frequency-hz = /bits/ 64 <2900000000>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <1>;
ad9081_dac0: dac@0 {
reg = <0>;
adi,crossbar-select = <&ad9081_tx_fddc_chan0>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
};
ad9081_dac1: dac@1 {
reg = <1>;
adi,crossbar-select = <&ad9081_tx_fddc_chan1>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
};
ad9081_dac2: dac@2 {
reg = <2>;
adi,crossbar-select = <&ad9081_tx_fddc_chan2>; /* All 4 channels @ dac2 */
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
};
ad9081_dac3: dac@3 {
reg = <3>;
adi,crossbar-select = <&ad9081_tx_fddc_chan3>; /* All 4 channels @ dac2 */
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <1>;
ad9081_tx_fddc_chan0: channel@0 {
reg = <0>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan1: channel@1 {
reg = <1>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan2: channel@2 {
reg = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan3: channel@3 {
reg = <3>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
ad9081_tx_jesd_l0: link@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adi,logical-lane-mapping = /bits/ 8 <0 2 7 7 1 7 7 3>;
adi,link-mode = <35>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <2>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <4>; /* JESD M */
adi,octets-per-frame = <3>; /* JESD F */
adi,frames-per-multiframe = <256>; /* JESD K */
adi,converter-resolution = <12>; /* JESD N */
adi,bits-per-sample = <12>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <8>; /* JESD L */
adi,samples-per-converter-per-frame = <4>; /* JESD S */
adi,high-density = <1>; /* JESD HD */
adi,tpl-phase-adjust = <0x3>;
};
};
};
adi,rx-adcs {
#size-cells = <0>;
#address-cells = <1>;
adi,adc-frequency-hz = /bits/ 64 <1450000000>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
ad9081_adc0: adc@0 {
reg = <0>;
adi,decimation = <1>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
adi,digital-gain-6db-enable;
//adi,crossbar-select = <&ad9081_rx_fddc_chan0>, <&ad9081_rx_fddc_chan2>; /* Static for now */
};
ad9081_adc1: adc@1 {
reg = <1>;
adi,decimation = <1>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
adi,digital-gain-6db-enable;
//adi,crossbar-select = <&ad9081_rx_fddc_chan1>, <&ad9081_rx_fddc_chan3>; /* Static for now */
};
ad9081_adc2: adc@2 {
reg = <2>;
adi,decimation = <1>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
adi,digital-gain-6db-enable;
//adi,crossbar-select = <&ad9081_rx_fddc_chan4>, <&ad9081_rx_fddc_chan6>; /* Static for now */
};
ad9081_adc3: adc@3 {
reg = <3>;
adi,decimation = <1>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
adi,digital-gain-6db-enable;
//adi,crossbar-select = <&ad9081_rx_fddc_chan5>, <&ad9081_rx_fddc_chan7>; /* Static for now */
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
ad9081_rx_fddc_chan0: channel@0 {
reg = <0>;
adi,decimation = <1>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
adi,digital-gain-6db-enable;
};
ad9081_rx_fddc_chan1: channel@1 {
reg = <1>;
adi,decimation = <1>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
adi,digital-gain-6db-enable;
};
ad9081_rx_fddc_chan4: channel@4 {
reg = <4>;
adi,decimation = <1>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
adi,digital-gain-6db-enable;
};
ad9081_rx_fddc_chan5: channel@5 {
reg = <5>;
adi,decimation = <1>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
adi,digital-gain-6db-enable;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
ad9081_rx_jesd_l0: link@0 {
reg = <0>;
adi,converter-select =
<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>,
<&ad9081_rx_fddc_chan4 FDDC_I>, <&ad9081_rx_fddc_chan4 FDDC_Q>,
<&ad9081_rx_fddc_chan5 FDDC_I>, <&ad9081_rx_fddc_chan5 FDDC_Q>;
adi,logical-lane-mapping = /bits/ 8 <2 0 7 7 7 7 3 1>;
adi,link-mode = <25>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <2>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <4>; /* JESD M */
adi,octets-per-frame = <6>; /* JESD F */
adi,frames-per-multiframe = <128>; /* JESD K */
adi,converter-resolution = <12>; /* JESD N */
adi,bits-per-sample = <12>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <4>; /* JESD L */
adi,samples-per-converter-per-frame = <4>; /* JESD S */
adi,high-density = <1>; /* JESD HD */
};
};
};
};
};
&axi_ad9081_core_tx {
single-shot-output-gpios = <&gpio 139 0>;
};
The FPGA system_project.tcl modifed to be:
adi_project ad9081_fmca_ebz_zcu102 0 [list \
JESD_MODE [get_env_param JESD_MODE 64B66B ] \
RX_LANE_RATE [get_env_param RX_LANE_RATE 17.96] \
TX_LANE_RATE [get_env_param TX_LANE_RATE 17.96 ] \
RX_JESD_M [get_env_param RX_JESD_M 4 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
RX_JESD_S [get_env_param RX_JESD_S 2 ] \
RX_JESD_NP [get_env_param RX_JESD_NP 12 ] \
RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
RX_TPL_WIDTH [get_env_param RX_TPL_WIDTH {} ] \
TX_JESD_M [get_env_param TX_JESD_M 4 ] \
TX_JESD_L [get_env_param TX_JESD_L 8 ] \
TX_JESD_S [get_env_param TX_JESD_S 4 ] \
TX_JESD_NP [get_env_param TX_JESD_NP 12 ] \
TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
TX_TPL_WIDTH [get_env_param TX_TPL_WIDTH {} ] \
TDD_SUPPORT [get_env_param TDD_SUPPORT 0 ] \
SHARED_DEVCLK [get_env_param SHARED_DEVCLK 0 ] \
TDD_CHANNEL_CNT [get_env_param TDD_CHANNEL_CNT 2 ] \
TDD_SYNC_WIDTH [get_env_param TDD_SYNC_WIDTH 32 ] \
TDD_SYNC_INT [get_env_param TDD_SYNC_INT 1 ] \
TDD_SYNC_EXT [get_env_param TDD_SYNC_EXT 0 ] \
TDD_SYNC_EXT_CDC [get_env_param TDD_SYNC_EXT_CDC 0 ] \
]
The jesd_status -s gives me:
The clk_summary is
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle nshot enable
--------------------------------------------------------------------------------------------------------------
clkin2_0 0 0 0 0 0 0 50000 0
Y
clkin1_0 0 0 0 0 0 0 50000 0
Y
si570_mgt 0 0 0 148499999 0 0 50000 0
Y
si570_user 0 0 0 299999998 0 0 50000 0
Y
hmc7044_out13 0 0 0 2832031 0 0 50000 0
Y
hmc7044_out12 2 2 0 181250000 0 0 50000 0
Y
tx_gt_clk 0 0 0 3625000 0 0 50000 0
?
tx_out_clk 0 0 0 54924242 0 0 50000 0
Y
rx_gt_clk 0 0 0 0 0 0 50000 0
?
rx_out_clk 0 0 0 0 0 0 50000 0
Y
hmc7044_out10 0 0 0 181250000 0 0 50000 0
Y
hmc7044_out8 0 0 0 181250000 0 0 50000 0
Y
hmc7044_out6 0 0 0 181250000 0 0 50000 0
Y
hmc7044_out3 0 0 0 2832031 0 0 50000 0
Y
hmc7044_out2 2 2 0 362500000 0 0 50000 0
Y
spi1.0-tx_sampl_clk 1 1 0 2900000000 0 0 50000 0
Y
spi1.0-rx_sampl_clk 0 0 0 1450000000 0 0 50000 0
Y
hmc7044_out0 0 0 0 120833333 0 0 50000 0
Y
refhdmi 1 1 0 114285000 0 0 50000 0
Y
xtal_0 0 0 0 114285000 0 0 50000 0
Y
pll_0 0 0 0 40731174000000 0 0 50000 0
Y
clk1_0 0 0 0 27000000 0 0 50000 0
Y
clk0_0 0 0 0 27000000 0 0 50000 0
Y
ref48M 2 2 0 48000000 0 0 50000 0
Y
si5341 3 3 0 14000000 0 0 50000 0
Y
clock-generator.N4 0 0 0 0 0 0 50000 0
Y
clock-generator.N3 0 0 0 0 0 0 50000 0
Y
clock-generator.N2 1 1 0 104000000 0 0 50000 0
Y
clock-generator.2 1 2 0 26000000 0 0 50000 0
Y
clock-generator.N1 1 2 0 594000000 0 0 50000 0
Y
clock-generator.7 0 1 0 74250000 0 0 50000 0
Y
clock-generator.0 1 2 0 27000000 0 0 50000 0
Y
clock-generator.N0 1 5 0 1000000000 0 0 50000 0
Y
clock-generator.9 0 1 0 33333333 0 0 50000 0
Y
clock-generator.8 0 0 0 0 0 0 50000 0
Y
clock-generator.6 0 1 0 125000000 0 0 50000 0
Y
clock-generator.5 0 1 0 100000000 0 0 50000 0
Y
clock-generator.4 0 1 0 100000000 0 0 50000 0
Y
clock-generator.3 1 2 0 125000000 0 0 50000 0
Y
clock-generator.1 0 0 0 0 0 0 50000 0
Y
aux_ref_clk 0 0 0 27000000 0 0 50000 0
Y
gt_crx_ref_clk 0 0 0 108000000 0 0 50000 0
Y
pss_alt_ref_clk 0 0 0 0 0 0 50000 0
Y
video_clk 0 0 0 27000000 0 0 50000 0
Y
pss_ref_clk 3 3 3 33333333 0 0 50000 0
Y
vpll_post_src 0 0 0 33333333 0 0 50000 0
Y
vpll_pre_src 1 1 1 33333333 0 0 50000 0
Y
vpll_int 1 1 1 1781999697 0 0 50000 0
Y
vpll_half 1 1 1 890999848 0 0 50000 0
Y
vpll_int_mux 1 1 1 890999848 0 0 50000 0
Y
vpll 1 1 1 890999848 0 0 50000 0
Y
dp_video_ref_mux 1 1 1 890999848 0 0 50000 0
Y
dp_video_ref_div1 1 1 1 148499975 0 0 50000 0
Y
dp_video_ref_div2 1 1 1 148499975 0 0 50000 0
Y
dp_video_ref 1 1 1 148499975 0 0 50000 0
Y
vpll_to_lpd 0 0 0 296999950 0 0 50000 0
Y
dpll_post_src 0 0 0 33333333 0 0 50000 0
Y
dpll_pre_src 0 0 0 33333333 0 0 50000 0
Y
dpll_int 0 0 0 2099999979 0 0 50000 0
Y
dpll_half 0 0 0 1049999989 0 0 50000 0
Y
dpll_int_mux 0 0 0 1049999989 0 0 50000 0
Y
dpll 0 0 0 1049999989 0 0 50000 0
Y
dpll_to_lpd 0 0 0 524999995 0 0 50000 0
Y
apll_post_src 0 0 0 33333333 0 0 50000 0
Y
apll_pre_src 1 1 1 33333333 0 0 50000 0
Y
apll_int 1 1 1 2399999976 0 0 50000 0
Y
apll_half 1 1 1 1199999988 0 0 50000 0
Y
apll_int_mux 1 1 1 1199999988 0 0 50000 0
Y
apll 1 1 1 1199999988 0 0 50000 0
Y
dpdma_ref_mux 1 1 1 1199999988 0 0 50000 0
Y
dpdma_ref_div1 1 1 1 599999994 0 0 50000 0
Y
dpdma_ref 1 1 1 599999994 0 0 50000 0
Y
gdma_ref_mux 0 0 0 1199999988 0 0 50000 0
Y
gdma_ref_div1 0 0 0 599999994 0 0 50000 0
Y
gdma_ref 0 0 0 599999994 0 0 50000 0
N
acpu_mux 0 0 0 1199999988 0 0 50000 0
Y
acpu 0 0 0 1199999988 0 0 50000 0
Y
rpll_post_src 0 0 0 33333333 0 0 50000 0
Y
rpll_pre_src 0 0 0 33333333 0 0 50000 0
Y
rpll_int 0 0 0 2399999976 0 0 50000 0
N
rpll_half 0 0 0 1199999988 0 0 50000 0
Y
rpll_int_mux 0 0 0 1199999988 0 0 50000 0
Y
rpll 0 0 0 1199999988 0 0 50000 0
Y
spi1_ref_mux 0 0 0 1199999988 0 0 50000 0
Y
spi1_ref_div1 0 0 0 99999999 0 0 50000 0
Y
spi1_ref_div2 0 0 0 99999999 0 0 50000 0
Y
spi1_ref 0 0 0 99999999 0 0 50000 0
N
spi0_ref_mux 0 0 0 1199999988 0 0 50000 0
Y
spi0_ref_div1 0 0 0 99999999 0 0 50000 0
Y
spi0_ref_div2 0 0 0 99999999 0 0 50000 0
Y
spi0_ref 0 0 0 99999999 0 0 50000 0
N
rpll_to_fpd 0 0 0 22641510 0 0 50000 0
Y
dp_stc_ref_mux 0 0 0 22641510 0 0 50000 0
Y
dp_stc_ref_div1 0 0 0 1509434 0 0 50000 0
Y
dp_stc_ref_div2 0 0 0 1509434 0 0 50000 0
Y
dp_stc_ref 0 0 0 1509434 0 0 50000 0
Y
dp_audio_ref_mux 0 0 0 22641510 0 0 50000 0
Y
dp_audio_ref_div1 0 0 0 22641510 0 0 50000 0
Y
dp_audio_ref_div2 0 0 0 22641510 0 0 50000 0
Y
dp_audio_ref 0 0 0 22641510 0 0 50000 0
N
iopll_post_src 0 0 0 33333333 0 0 50000 0
Y
iopll_pre_src 1 1 1 33333333 0 0 50000 0
Y
iopll_int 1 1 1 2999999970 0 0 50000 0
Y
iopll_half 1 1 1 1499999985 0 0 50000 0
Y
iopll_int_mux 1 1 1 1499999985 0 0 50000 0
Y
iopll 14 17 11 1499999985 0 0 50000 0
Y
gem3_ref_ung_mux 1 1 0 1499999985 0 0 50000 0
Y
gem3_ref_ung_div1 1 1 0 1499999985 0 0 50000 0
Y
gem3_ref_ung 1 1 0 124999999 0 0 50000 0
Y
gem3_ref 2 2 0 124999999 0 0 50000 0
Y
gem3_tx 1 1 0 124999999 0 0 50000 0
Y
gem2_ref_ung_mux 0 0 0 1499999985 0 0 50000 0
Y
gem2_ref_ung_div1 0 0 0 62500000 0 0 50000 0
Y
gem2_ref_ung 0 0 0 62500000 0 0 50000 0
Y
gem2_ref 0 0 0 62500000 0 0 50000 0
Y
gem2_tx 0 0 0 62500000 0 0 50000 0
Y
gem1_ref_ung_mux 0 0 0 1499999985 0 0 50000 0
Y
gem1_ref_ung_div1 0 0 0 62500000 0 0 50000 0
Y
gem1_ref_ung 0 0 0 62500000 0 0 50000 0
Y
gem1_ref 0 0 0 62500000 0 0 50000 0
Y
gem1_tx 0 0 0 62500000 0 0 50000 0
Y
gem0_ref_ung_mux 0 0 0 1499999985 0 0 50000 0
Y
gem0_ref_ung_div1 0 0 0 62500000 0 0 50000 0
Y
gem0_ref_ung 0 0 0 62500000 0 0 50000 0
Y
gem0_ref 0 0 0 62500000 0 0 50000 0
Y
gem0_tx 0 0 0 62500000 0 0 50000 0
Y
pl3_ref_mux 1 1 0 1499999985 0 0 50000 0
Y
pl3_ref_div1 1 1 0 46875000 0 0 50000 0
Y
pl3_ref_div2 1 1 0 9375000 0 0 50000 0
Y
pl3_ref 1 1 0 9375000 0 0 50000 0
Y
pl2_ref_mux 1 1 0 1499999985 0 0 50000 0
Y
pl2_ref_div1 1 1 0 499999995 0 0 50000 0
Y
pl2_ref_div2 1 1 0 499999995 0 0 50000 0
Y
pl2_ref 3 3 0 499999995 0 0 50000 0
Y
pl1_ref_mux 1 1 0 1499999985 0 0 50000 0
Y
pl1_ref_div1 1 1 0 249999998 0 0 50000 0
Y
pl1_ref_div2 1 1 0 249999998 0 0 50000 0
Y
pl1_ref 1 1 0 249999998 0 0 50000 0
Y
pl0_ref_mux 1 1 0 1499999985 0 0 50000 0
Y
pl0_ref_div1 1 1 0 99999999 0 0 50000 0
Y
pl0_ref_div2 1 1 0 99999999 0 0 50000 0
Y
pl0_ref 3 3 0 99999999 0 0 50000 0
Y
ams_ref_mux 1 1 1 1499999985 0 0 50000 0
Y
ams_ref_div1 1 1 1 50000000 0 0 50000 0
Y
ams_ref_div2 1 1 1 50000000 0 0 50000 0
Y
ams_ref 1 1 1 50000000 0 0 50000 0
Y
adma_ref_mux 0 0 0 1499999985 0 0 50000 0
Y
adma_ref_div1 0 0 0 499999995 0 0 50000 0
Y
adma_ref 0 0 0 499999995 0 0 50000 0
Y
can1_ref_mux 0 0 0 1499999985 0 0 50000 0
Y
can1_ref_div1 0 0 0 99999999 0 0 50000 0
Y
can1_ref_div2 0 0 0 99999999 0 0 50000 0
Y
can1_ref 0 0 0 99999999 0 0 50000 0
N
can1 0 0 0 99999999 0 0 50000 0
Y
can0_ref_mux 0 0 0 1499999985 0 0 50000 0
Y
can0_ref_div1 0 0 0 46875000 0 0 50000 0
Y
can0_ref_div2 0 0 0 46875000 0 0 50000 0
Y
can0_ref 0 0 0 46875000 0 0 50000 0
Y
can0 0 0 0 46875000 0 0 50000 0
Y
i2c1_ref_mux 0 1 1 1499999985 0 0 50000 0
Y
i2c1_ref_div1 0 1 1 99999999 0 0 50000 0
Y
i2c1_ref_div2 0 1 1 99999999 0 0 50000 0
Y
i2c1_ref 0 1 1 99999999 0 0 50000 0
N
i2c0_ref_mux 0 1 1 1499999985 0 0 50000 0
Y
i2c0_ref_div1 0 1 1 99999999 0 0 50000 0
Y
i2c0_ref_div2 0 1 1 99999999 0 0 50000 0
Y
i2c0_ref 0 1 1 99999999 0 0 50000 0
N
nand_ref_mux 0 0 0 1499999985 0 0 50000 0
Y
nand_ref_div1 0 0 0 46875000 0 0 50000 0
Y
nand_ref_div2 0 0 0 9375000 0 0 50000 0
Y
nand_ref 0 0 0 9375000 0 0 50000 0
N
uart1_ref_mux 0 1 1 1499999985 0 0 50000 0
Y
uart1_ref_div1 0 1 1 99999999 0 0 50000 0
Y
uart1_ref_div2 0 1 1 99999999 0 0 50000 0
Y
uart1_ref 0 1 1 99999999 0 0 50000 0
N
uart0_ref_mux 1 1 1 1499999985 0 0 50000 0
Y
uart0_ref_div1 1 1 1 99999999 0 0 50000 0
Y
uart0_ref_div2 1 1 1 99999999 0 0 50000 0
Y
uart0_ref 1 1 1 99999999 0 0 50000 0
Y
sdio1_ref_mux 1 1 1 1499999985 0 0 50000 0
Y
sdio1_ref_div1 1 1 1 187499999 0 0 50000 0
Y
sdio1_ref_div2 1 1 1 187499999 0 0 50000 0
Y
sdio1_ref 1 1 1 187499999 0 0 50000 0
Y
clk_in_sd1 0 0 0 50000000 0 0 50000 0
Y
clk_out_sd1 0 0 0 50000000 0 0 50000 0
Y
sdio0_ref_mux 0 0 0 1499999985 0 0 50000 0
Y
sdio0_ref_div1 0 0 0 99999999 0 0 50000 0
Y
sdio0_ref_div2 0 0 0 99999999 0 0 50000 0
Y
sdio0_ref 0 0 0 99999999 0 0 50000 0
Y
qspi_ref_mux 1 1 1 1499999985 0 0 50000 0
Y
qspi_ref_div1 1 1 1 124999999 0 0 50000 0
Y
qspi_ref_div2 1 1 1 124999999 0 0 50000 0
Y
qspi_ref 1 1 1 124999999 0 0 50000 0
Y
gem_tsu_ref_mux 1 1 1 1499999985 0 0 50000 0
Y
gem_tsu_ref_div1 1 1 1 249999998 0 0 50000 0
Y
gem_tsu_ref_div2 1 1 1 249999998 0 0 50000 0
Y
gem_tsu_ref 1 1 1 249999998 0 0 50000 0
Y
gem_tsu 1 1 0 249999998 0 0 50000 0
Y
usb3_dual_ref_mux 1 1 1 1499999985 0 0 50000 0
Y
usb3_dual_ref_div1 1 1 1 60000000 0 0 50000 0
Y
usb3_dual_ref_div2 1 1 1 20000000 0 0 50000 0
Y
usb3_dual_ref 2 2 2 20000000 0 0 50000 0
Y
usb1_bus_ref_mux 0 0 0 1499999985 0 0 50000 0
Y
usb1_bus_ref_div1 0 0 0 124999999 0 0 50000 0
Y
usb1_bus_ref_div2 0 0 0 124999999 0 0 50000 0
Y
usb1_bus_ref 0 0 0 124999999 0 0 50000 0
N
usb0_bus_ref_mux 1 1 1 1499999985 0 0 50000 0
Y
usb0_bus_ref_div1 1 1 1 249999998 0 0 50000 0
Y
usb0_bus_ref_div2 1 1 1 249999998 0 0 50000 0
Y
usb0_bus_ref 1 1 1 249999998 0 0 50000 0
Y
lpd_lsbus_mux 1 1 0 1499999985 0 0 50000 0
Y
lpd_lsbus_div1 1 1 0 99999999 0 0 50000 0
Y
lpd_lsbus 7 8 0 99999999 0 0 50000 0
Y
lpd_wdt 0 0 0 99999999 0 0 50000 0
Y
iopll_to_fpd 3 3 2 499999995 0 0 50000 0
Y
topsw_lsbus_mux 1 1 0 499999995 0 0 50000 0
Y
topsw_lsbus_div1 1 1 0 99999999 0 0 50000 0
Y
topsw_lsbus 4 4 0 99999999 0 0 50000 0
Y
fpd_wdt 1 1 0 99999999 0 0 50000 0
Y
gpu_ref_mux 0 0 0 499999995 0 0 50000 0
Y
gpu_ref_div1 0 0 0 499999995 0 0 50000 0
Y
gpu_ref 0 0 0 499999995 0 0 50000 0
Y
gpu_pp1_ref 0 0 0 499999995 0 0 50000 0
N
gpu_pp0_ref 0 0 0 499999995 0 0 50000 0
N
pcie_ref_mux 1 1 1 499999995 0 0 50000 0
Y
pcie_ref_div1 1 1 1 249999998 0 0 50000 0
Y
pcie_ref 1 1 1 249999998 0 0 50000 0
Y
sata_ref_mux 1 1 1 499999995 0 0 50000 0
Y
sata_ref_div1 1 1 1 249999998 0 0 50000 0
Y
sata_ref 1 1 1 249999998 0 0 50000 0
Y
can1_mio 0 0 0 0 0 0 50000 0
Y
can0_mio 0 0 0 0 0 0 50000 0
Y
gem3_rx 1 1 0 0 0 0 50000 0
Y
gem2_rx 0 0 0 0 0 0 50000 0
N
gem1_rx 0 0 0 0 0 0 50000 0
N
gem0_rx 0 0 0 0 0 0 50000 0
N
Any help would be greatly appreciated.
Hi,
It looks like you are trying to implement FBW mode for both TX and RX without any interpolation and decimation, then I see some issues in your device tree (and possibly HDL as well).
For example, if you use JESD mode 25 for ADC path, then you have only the following options as specified in the user guide.
Only the first line in the table is FBW mode, and in this case the lane rate cannot be lower than 16 Gbps. In order to keep it below, you need to have a different mode with either higher L or lower M. For example, you may be able to implement mode 28 with L=8 and M=4.
Please note that all CDDC and FDDC are bypassed in FBW with decimation ratio of 1x1 and it doesn't make sense to have M bigger than 4. Same rules apply to TX path as well.
Please review the mode tables in the user guide. We should be able help you once you determine your target configuration consistent with the table.
-YH
Thank you for the detailed response. I think in order to meet both the lane rate maximum and the dac rate minimum, I have to settle for 2 DAC channels. I have changed to TX mode 18 and TX mode 19. Lane rate is 11.9625, DAC and ADC rates are both 2.9. This build does appear to be working as the jesd_status looks clean and I don't see any errors in the kernel log
I am using the pyadi-iio library but it's giving me some errors on initialization. I will open a ticket on the Software Interface Tools board.
Traceback (most recent call last):
File "/home/analog/randomized_switching_generator_JA203.py", line 335, in <module>
sdr = adi.ad9081()
File "/usr/local/lib/python3.9/dist-packages/adi/ad9081.py", line 145, in __init__
self._rx_coarse_ddc_channel_names.append(channels[0])
IndexError: list index out of range
If I use the DAC buffer output with the sinewave matlab file, it seems there is a 300nS gap between bursts.
I am able to use the tone generator in the oscilloscope program and it generates a continuous waveform properly.
When I use the pyadi tx function with a single cycle generated sine wave pattern in tx cyclic buffer mode, I also see the same 300ns gap but only between each cycle. Is this just a latency issue between the computer and the IC?
