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Pluto/AD9363 Transmit-Receive Synchronism (FDD Mode)

Category: Software
Product Number: Pluto
Software Version: PlutoSDR Rev.C (Z7010-AD9363A) v0.38 Linux pluto 5.15.0-175882-ge14e351533f9 plutosdr-fw-v0.38 Libiio version: 0.25

Hi All,

I have an application that requires synchronization between Pluto/AD9363 transmit and receive waveforms while operating in FDD mode.

Despite experimentation using the classes available under pyadi-iio/adi/ad936x.py and related pyadi-iio/adi/rx_tx.py etc., I have not yet found an obvious way to achieve this. This conclusion applies whether I use e.g. cyclic or “single shot” transmission configuration.

I note the use of pyadi-iio/adi/tddn.py and the companion AXI TDD controller IP for transmit-receive timing control in TDD mode, but since I wish to operate in ENSM FDD mode, I believe this is inapplicable.

Unfortunately, my review of the history of related questions in this forum – e.g., “Implementing Radar with Pluto SDR” from May 2020 (https://ez.analog.com/linux-software-drivers/f/q-a/166234/implementing-radar-with-pluto-sdr) – points to designs that require HDL reconfiguration such as “Loopback Delay Estimation Design” (https://wiki.analog.com/loopback_delay_estimation), with undesirable HDL tool expense and complexity.

Before I consider HDL changes or enabling the less elegant approach of synchronization via transmit port coupling to receive port, can anyone advise of there is a way to use PyADI-IIO classes to ensure a deterministic timing relationship between Pluto/AD9363 transmit and receive ports in FDD mode within the scope of any available ADI libiio software (e.g., v0.25) or pluto firmware (e.g. 0.38) or (Rev-C or -D) release?

Many thanks for any comments - much appreciated!

-Ken

  • Well, I don't think the TDD engine only works in EMSM TDD mode.

    It can do the DMA gating and the ENSM pin control. But there shouldn't be anything that prevents you to omit the pin control.

    There is very soon a new plutosdr-fw release which has the latest TDD engine, used on the phasor design. Stay tuned.

    -Michael

  • Many thanks  for the comment, Michael.

    Before configuring and triggering the TDD state machine, the online examples I have reviewed that use class tddn() first invoke:

    sdr._ctrl.debug_attrs["adi,frequency-division-duplex-mode-enable"].value = "0"

    resulting in the ENSM mode available change from:

    ensm_mode_available: sleep wait alert fdd pinctrl pinctrl_fdd_indep

    to

    ensm_mode_available: sleep wait alert rx tx pinctrl

    Hence my assumption regarding the FDD limitation on AXI TDD block sequencing.

    I will attempt again, however, to trigger the TDD state machine according to my timing requirements while retaining the baseline ENSM mode that includes FDD operation. If anyone can point to a successful published example of this, I'd be grateful.

    And thanks also to Michael for the heads-up on the new plutosdr-fw release.

    -Ken