Multichip Synchroniztion

Hi,

As it is the MCS can't work propperly on zedboard.
The reference clock is not connected in the system for the zedboard.
I have some updates to the HDL MCS flow. I will test the MCS on zed.
But this might take a few days, I will probably have something by the end of the week.

Andrei

Hi, Andrei If you have some on ideas to try can you let us know, we would like try it in parallel on our Zedboard platform.

1. As MCS is one of the main requirements of out project (we are using adrv9002 on Zedboard), we tested MCS on ZCU102 LVDS version of project and it was successful.
2. We moved a step further to test MCS on CMOS version of ZCU102 (followed same procedure as it was in case of LVDS) but we faced timeout error.
3. One thing that I have noticed is that both LVDS and CMOS versions of ZCU102 HDL projects have fpga_ref_clk and dev_mcs_fpga_out ports connected as LVDS. should these be connected as CMOS in for CMOS HDL version?
4. Also one thing to notice is that TES GUI has only fix LVDS standard for reference clock for both LVDS and CMOS SSI Type. But MCS interface changes to CMOS and LVDS according to SSI type selected. 

Comming with an update: MCS for CMOS also works on ZCU102 with some changes 

1. Change in RTL to convert differential mcs signal to single ended

   assign dev_mcs_fpga_out_p = dev_mcs_fpga_in ;
   assign dev_mcs_fpga_out_n = 1'b0 ;

2. Change the io standard to LVCMOS

  set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18} [get_ports dev_mcs_fpga_out_n] ; #FMC_HPC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66
  set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18} [get_ports dev_mcs_fpga_out_p] ; #FMC_HPC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66