Tunneling mode configuration question TUN_DEST

Hi :),

 I'm tying to configure the MAX96724. I've started with selection of "Pixel or Tunneling" mode, but I have a question about register 0x969 :

Target:

1) I want to enable "Tunneling mode" so I set the reg 0x0936 to 0x29.

2) I want to use automatic tunnel detection feature, so I've set reg 0x939 to 0x10 but I'm in case to use port B probably I should set is as 0x30

Question:

My question is about TUN_DEST bits - in one documentation I see the description of the reg TUN_DEST bits [5:4]  as:

"Bit [5:4]: TUN_DEST, Pipe to PHY mapping.
00 = PHY0
01 = PHY1
10 = PHY2
11 = PHY3"

and in DS I see the same reg description as:

"TUN_DEST 5:4 Tunneling controller Destination
0x0: Controller 0 "
0x1: Controller 1 "

I wanted to use "2x4 D-PHY Mode" and forward the data onto port B.

Which description of this above reg is proper?

Regarding below schematic how I should understand "PHYn" and "Cotroller n" in this reg? I'm selecting the "Controller n" or "PHY n" in this register?

To use use port B as a output to SoC  (with enabled auto tunneling mode detect.) I should set this 0x939 reg to 0x30 or ??

Please correct me if I'm wrong but I understand this in such way, that 0x939 with value 0x10 will "send" data from video pipe 0 to "MIPI Controller 1" so below settings for 2x4 D-PHY Mode:

(des), 0x0939, 0x10 // MIPI_TX 0 (pipe 0 to Controller 1)
(des), 0x0979, 0x10 // MIPI_TX 1 (pipe 1 to Controller 1)
(des), 0x09B9, 0x10 // MIPI_TX 2 (pipe 2 to Controller 1)
(des), 0x09F9, 0x10 // MIPI_TX 3 (pipe 3 to Controller 1)

will "redirected" all four Video Pipes to Controller 1 which (in 2x4 D-PHY Mode) is controlling (MIPI PHY 0 and MIPI PHY 1) Port A (DA0 P/N - DA3 P/N).

But in mentioned 2x4 D-PHY Mode I have to also do a mapping all VP into MIPI PHY 1 (because it is a master in 2x4 mode)? Am I correct?