Dear Team,
I'm currently working with the ZCU102 and ADRV9008-1 & ADRV9008-2 Evaluation Boards to assess the ADC and DAC for our specific use case. We've successfully connected both the ADC and DAC cards to the ZCU102 and are able to generate and receive signals using the provided example design.
We've also developed a custom board using the same ADC and DAC components. However, on our board, the AD9528 Sysref_in Clock signals are not connected.
Upon examining the sysref signal state on the evaluation board, we made the following observations:
1. We traced the sysref_out signal from the FPGA design to the ADRV9008-1 Evaluation Board using the ZCU102 and ADRV9008-1 schematics, along with the Vivado code, and noted the following discrepancies:
a. In the Vivado design, the ports sysref_out_p & sysref_out_n are mapped to the AJ6 & AJ5 pins in the XDC (see the attached screenshot).
b. When we traced it to the FMC and evaluation board, we found that these pins are connected to SPI_CS0 of ADRV9008-1 & SPI_CS1 of AD9528 (our analysis is attached).
2. Similarly we traced the spi_csn_ad9528 & spi_csn_adrv9009 signal from the FPGA design to the ADRV9008-1 Evaluation Board using the ZCU102 and ADRV9008-1 schematics, along with the Vivado code, and noted the following discrepancies:
a. In the Vivado design, the ports spi_csn_ad9528 & spi_csn_adrv9009 are mapped to the AE1 & AE2 pins in the XDC (see the attached screenshot).
b. When we traced it to the FMC and evaluation board, we found that these pins are connected to SYSREF_IN & SYSREF_IN_N pins of AD9528 (our analysis is attached).
Queries :
1. It appears that the SPI CS and sysref_out signals are swapped according to the schematics and code. We would like to understand if we are missing something here.
2. since the AD9528 SYSREF_IN Clock signals are not connected on our custom board, I attempted to replicate this condition by not driving any input to the SYSREF_IN on the ZCU102 Evaluation Board. However, without the SYSREF_IN signal, I observed that the ADC and DAC clocks were not generated in the Vivado block design, and the overall design failed to operate. We would like to understand if there is something we are overlooking.
Note:
We are using the ADRV9009 Vivado project from the 2022 version available on GitHub and have modified it to suit our requirements.
The schematic versions for the ZCU102 and ADRV9008-1 are "HW-Z1-ZCU102_REVC" & "ADRV9008-1WPCBZ_Schematic_RevA", respectively.
