AD9081
Recommended for New Designs
The AD9081 mixed signal front end (MxFE®) is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter...
Datasheet
AD9081 on Analog.com
HMC7044
Recommended for New Designs
The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise...
Datasheet
HMC7044 on Analog.com
Hi everyone,
We have a ZCU102 to which we have connected an AD9081-FMCA-EBZ.
The version of the AD9081 board we have has the 100 MHz VCXO. For our purposes, we have replaced the 100 MHz oscillator with a 122.88 MHz oscillator.
In the end, we want the ADC and the DAC to sample at 122.88 MSPS.
We feed a 122.88 MHz signal from a signal generator into the CLKIN1 port of the HMC7044 as an external reference.
After adjusting the device tree, both PLLs now lock, but the AD9081 is no longer visible via iio:device.
I'm aware that the clocks of the remaining HMC7044 channels don't fit anymore, but how to make them fit again? Which values should we choose for the "adi,divider" values of the hmc7044 channels(e.g.: DEV_REFCLK, DEV_SYSREF, FPGA_REFCLK1)?
Right now, the CORE_CLK_TX and CORE_CLK_RX are set to 122.88 MHz
and adi,vcxo-frequency = 122.88 MHz, adi,pll1-clkin-frequencies = 122.88 MHz and PLL2 out is chosen as 2,949.120 MHz (122.88 MHz * 24).
dmesg:
[ 5.647585] ad9081 spi0.0: supply vdd not found, using dummy regulator [ 6.817987] ad9081 spi0.0: Invalid param passed., "adc_clk_hz > (device->dev_info.prod_id == 0x9081 ? 4000000000ULL : 6300000000ULL)" in adi_ad9081_device_clk_config_set(...), line595 in [ 6.835004] ad9081 spi0.0: Cannot find any settings to lock device PLL. [ 6.841617] ad9081 spi0.0: Failed to initialize: -14 [ 6.846579] ad9081: probe of spi0.0 failed with error -14
Below you will find the AD9081 and HMC7044 nodes in the device tree:
spi@ff040000 {
compatible = "cdns,spi-r1p6";
status = "okay";
interrupt-parent = <0x04>;
interrupts = <0x00 0x13 0x04>;
reg = <0x00 0xff040000 0x00 0x1000>;
clock-names = "ref_clk\0pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
power-domains = <0x0c 0x23>;
clocks = <0x03 0x3a 0x03 0x1f>;
phandle = <0xa1>;
ad9081@0 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reset-gpios = <0x15 0x85 0x00>;
sysref-req-gpios = <0x15 0x79 0x00>;
rx2-enable-gpios = <0x15 0x87 0x00>;
rx1-enable-gpios = <0x15 0x86 0x00>;
tx2-enable-gpios = <0x15 0x89 0x00>;
tx1-enable-gpios = <0x15 0x88 0x00>;
compatible = "adi,ad9082";
reg = <0x00>;
spi-max-frequency = <0x4c4b40>;
clocks = <0x1f 0x02>;
clock-names = "dev_clk";
clock-output-names = "rx_sampl_clk\0tx_sampl_clk";
#clock-cells = <0x01>;
jesd204-device;
#jesd204-cells = <0x02>;
jesd204-top-device = <0x00>;
jesd204-link-ids = <0x02 0x00>;
jesd204-inputs = <0x20 0x00 0x02 0x21 0x00 0x00>;
phandle = <0x43>;
adi,tx-dacs {
#size-cells = <0x00>;
#address-cells = <0x01>;
adi,dac-frequency-hz = <0x02 0xAFC80000>;
adi,main-data-paths {
#address-cells = <0x01>;
#size-cells = <0x00>;
adi,interpolation = <0x06>;
dac@0 {
reg = <0x00>;
adi,crossbar-select = <0x22>;
adi,nco-frequency-shift-hz = <0x00 0x3b9aca00>;
phandle = <0xa2>;
};
dac@1 {
reg = <0x01>;
adi,crossbar-select = <0x23>;
adi,nco-frequency-shift-hz = <0x00 0x4190ab00>;
phandle = <0xa3>;
};
};
adi,channelizer-paths {
#address-cells = <0x01>;
#size-cells = <0x00>;
adi,interpolation = <0x04>;
channel@0 {
reg = <0x00>;
adi,gain = <0x800>;
adi,nco-frequency-shift-hz = <0x00 0x00>;
phandle = <0x22>;
};
channel@1 {
reg = <0x01>;
adi,gain = <0x800>;
adi,nco-frequency-shift-hz = <0x00 0x00>;
phandle = <0x23>;
};
};
adi,jesd-links {
#size-cells = <0x00>;
#address-cells = <0x01>;
link@0 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x00>;
adi,logical-lane-mapping = <0x20706 0x1050403>;
adi,link-mode = <0x11>;
adi,subclass = <0x01>;
adi,version = <0x01>;
adi,dual-link = <0x00>;
adi,converters-per-device = <0x04>;
adi,octets-per-frame = <0x01>;
adi,frames-per-multiframe = <0x20>;
adi,converter-resolution = <0x10>;
adi,bits-per-sample = <0x10>;
adi,control-bits-per-sample = <0x00>;
adi,lanes-per-device = <0x08>;
adi,samples-per-converter-per-frame = <0x01>;
adi,high-density = <0x01>;
adi,tpl-phase-adjust = <0x06>;
phandle = <0xa4>;
};
};
};
adi,rx-adcs {
#size-cells = <0x00>;
#address-cells = <0x01>;
adi,adc-frequency-hz = <0x01 0xAFC80000>;
adi,main-data-paths {
#address-cells = <0x01>;
#size-cells = <0x00>;
adc@0 {
reg = <0x00>;
adi,decimation = <0x06>;
adi,nco-frequency-shift-hz = <0x00 0x3b9aca00>;
adi,nco-mixer-mode = <0x00>;
phandle = <0xa5>;
};
adc@1 {
reg = <0x01>;
adi,decimation = <0x06>;
adi,nco-frequency-shift-hz = <0x00 0x3b9aca00>;
adi,nco-mixer-mode = <0x00>;
phandle = <0xa6>;
};
};
adi,channelizer-paths {
#address-cells = <0x01>;
#size-cells = <0x00>;
channel@0 {
reg = <0x00>;
adi,decimation = <0x04>;
adi,gain = <0x800>;
adi,nco-frequency-shift-hz = <0x00 0x00>;
phandle = <0x24>;
};
channel@1 {
reg = <0x01>;
adi,decimation = <0x04>;
adi,gain = <0x800>;
adi,nco-frequency-shift-hz = <0x00 0x00>;
phandle = <0x25>;
};
};
adi,jesd-links {
#size-cells = <0x00>;
#address-cells = <0x01>;
link@0 {
reg = <0x00>;
adi,converter-select = <0x24 0x00 0x24 0x01 0x25 0x00 0x25 0x01>;
adi,logical-lane-mapping = <0x2000706 0x5040301>;
adi,link-mode = <0x12>;
adi,subclass = <0x01>;
adi,version = <0x01>;
adi,dual-link = <0x00>;
adi,converters-per-device = <0x04>;
adi,octets-per-frame = <0x01>;
adi,frames-per-multiframe = <0x20>;
adi,converter-resolution = <0x10>;
adi,bits-per-sample = <0x10>;
adi,control-bits-per-sample = <0x00>;
adi,lanes-per-device = <0x08>;
adi,samples-per-converter-per-frame = <0x01>;
adi,high-density = <0x01>;
phandle = <0xa7>;
};
};
};
};
};spi@ff050000 {
compatible = "cdns,spi-r1p6";
status = "okay";
interrupt-parent = <0x04>;
interrupts = <0x00 0x14 0x04>;
reg = <0x00 0xff050000 0x00 0x1000>;
clock-names = "ref_clk\0pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
power-domains = <0x0c 0x24>;
clocks = <0x03 0x3b 0x03 0x1f>;
phandle = <0xa8>;
hmc7044@0 {
#address-cells = <0x01>;
#size-cells = <0x00>;
#clock-cells = <0x01>;
compatible = "adi,hmc7044";
reg = <0x00>;
spi-max-frequency = <0xf4240>;
jesd204-device;
#jesd204-cells = <0x02>;
jesd204-sysref-provider;
adi,jesd204-max-sysref-frequency-hz = <0x1e8480>;
adi,pll1-clkin-frequencies = <0x7530000 0x7530000 0x00 0x00>;
adi,pll1-ref-prio-ctrl = <0xe1>;
adi,pll1-ref-autorevert-enable;
adi,vcxo-frequency = <0x7530000>;
adi,pll1-loop-bandwidth-hz = <0xc8>;
adi,pll1-charge-pump-current-ua = <0x2d0>;
adi,pfd1-maximum-limit-frequency-hz = <0xf4240>;
adi,pll2-output-frequency = <0xAFC80000>;
adi,sysref-timer-divider = <0x400>;
adi,pulse-generator-mode = <0x00>;
adi,clkin0-buffer-mode = <0x07>;
adi,clkin1-buffer-mode = <0x07>;
adi,oscin-buffer-mode = <0x15>;
adi,gpi-controls = <0x00 0x00 0x00 0x00>;
adi,gpo-controls = <0x37 0x33 0x00 0x00>;
clock-output-names = "hmc7044_out0\0hmc7044_out1\0hmc7044_out2\0hmc7044_out3\0hmc7044_out4\0hmc7044_out5\0hmc7044_out6\0hmc7044_out7\0hmc7044_out8\0hmc7044_out9\0hmc7044_out10\0hmc7044_out11\0hmc7044_out12\0hmc7044_out13";
phandle = <0x1f>;
channel@0 {
reg = <0x00>;
adi,extended-name = "CORE_CLK_RX";
adi,divider = <0x18>;
adi,driver-mode = <0x02>;
phandle = <0xa9>;
};
channel@2 {
reg = <0x02>;
adi,extended-name = "DEV_REFCLK";
adi,divider = <0x0c>;
adi,driver-mode = <0x02>;
phandle = <0xaa>;
};
channel@3 {
reg = <0x03>;
adi,extended-name = "DEV_SYSREF";
adi,divider = <0x600>;
adi,driver-mode = <0x02>;
adi,jesd204-sysref-chan;
phandle = <0xab>;
};
channel@6 {
reg = <0x06>;
adi,extended-name = "CORE_CLK_TX";
adi,divider = <0x18>;
adi,driver-mode = <0x02>;
phandle = <0xac>;
};
channel@8 {
reg = <0x08>;
adi,extended-name = "FPGA_REFCLK1";
adi,divider = <0x06>;
adi,driver-mode = <0x02>;
phandle = <0xad>;
};
channel@10 {
reg = <0x0a>;
adi,extended-name = "CORE_CLK_RX_ALT";
adi,divider = <0x18>;
adi,driver-mode = <0x02>;
phandle = <0xae>;
};
channel@12 {
reg = <0x0c>;
adi,extended-name = "FPGA_REFCLK2";
adi,divider = <0x04>;
adi,driver-mode = <0x02>;
phandle = <0xaf>;
};
channel@13 {
reg = <0x0d>;
adi,extended-name = "FPGA_SYSREF";
adi,divider = <0x600>;
adi,driver-mode = <0x02>;
adi,jesd204-sysref-chan;
phandle = <0xb0>;
};
};
};Thanks in advance!
Regards
